You can view the following DRAM timing configuration values:
| Parameter | Description |
|---|---|
| Tcl | CAS Latency |
| Trcd | Row Address to Column Address Delay |
| Trp | Row Precharge Delay |
| Tras | RAS Active Time |
| Trc | Row Cycle Time |
| Trfc | Refresh Recovery Delay Time |
| Tfaw | Four Activate Windows Time |
| TrrdS | Activate to Activate Delay Time, different bank group (tRRD_S) |
| TrrdL | Activate to Activate Delay Time, same bank group (tRRD_L) |
| Twr | Minimum Write Recovery Time |
| TwtrS | Minimum Write to Read Time, different bank group |
| TwtrL | Minimum Write to Read Time, same bank group |
| Trtp | Read CAS# to precharge time |
| TrdrdSc | Read to Read timing same chip select |
| TrdrdScL | Read to Read timing same chip select same bank group |
| TrdrdSd | Read to Read timing same DIMM |
| TrdrdDd | Read to Read timing different DIMM |
| TwrwrSc | Write to Write timing same chip select |
| TwrwrScL | Write to Write timing same chip select same bank group |
| TwrwrSd | Write to Write timing same DIMM |
| TwrwrDd | Write to Write timing different DIMM |
| Trdwr | Read to Write timing |
| TrfcSb | Refresh Recovery Delay Time |
| Twrrd | Write to read timing |