By leveraging on-chip hardware counters, AMD uProf can help developers understand performance bottlenecks and tune their applications for maximum efficiency. This section provides an overview of how to generate and view hardware counter data using AMD uProf, including basic concepts, configuration options, and common pitfalls.
AMD uProf has two hardware counter sampling modes. In one, data is collected using event-based profiling (EBP) which samples traditional core PMCs (performance monitoring counters). Core PMCs are those located on each logical processor core. These exclude the uncore PMCs which collect data from L3 caches and the data fabric, which can be accessed using uProfPcm. The other sampling mode is Instruction-Based Sampling (IBS).
It is not possible to combine EBP and IBS, or to use either with hotspots analysis. The alternative TBP method is compatible with EBP using multiplexing. The call stack reconstruction methods available with TBP (using frame pointers or DWARF data) are typically unreliable and should be used with care, or not at all.
AMD uProf provides various predefined profile configurations for use with EBP. These are a good place to start as they contain useful sets of counters for initial analyses to identify which performance bottlenecks are in play, and also include sets of PMCs for deeper analyses of specific issues.