How do I evaluate if my design is impacted during power-on? - How do I evaluate if my design is impacted during power-on?

If the answers to ALL three of the following power-on test questions are NO, then the PS eFUSE integrity might be impacted during power-on.

See the "When further analysis is needed" section below.

• Power-on test 1: Does PS_POR_B meet the datasheet requirements for power-on and is asserted low (GND) until V_CCPINT, V_CCPAUX , and V_{CCO_MIO0} have reached their minimum voltage levels? If YES, then NO RISK. Passing this test is represented in solution 1.
• Power-on test 2: Is the PS reference clock (PS_CLK) inactive until V_CCPINT has reached 0.80V? If YES, then NO RISK. Passing this test is represented in solution 2.
• Power-on test 3: Does the power supply sequence follow the recommended power-on sequence (1: V_CCPINT, 2: V_CCPAUX, 3: V_{CCO_MIO0})?
  V_CCPINT must reach 0.80V before both V_CCPAUX reaches 0.70V and V_{CCO_MIO0} reaches 0.90V.
  If YES, then NO RISK. Passing this test is represented in solution 3.