AOCL-DLP automatically selects the best kernel for your CPU based on available instruction sets. However, you can override this behavior for testing or specific optimization scenarios.
Architecture Control:
The AOCL_ENABLE_INSTRUCTIONS environment variable forces specific instruction sets, overriding auto-detection:
# Force AVX512 instructions on Zen4 processors
export AOCL_ENABLE_INSTRUCTIONS=avx512
./your_application
# Use Zen3-optimized kernels
export AOCL_ENABLE_INSTRUCTIONS=zen3
./your_application
Supported Values (case-insensitive):
Value |
Description |
|---|---|
|
Zen 5 architecture optimizations (AVX512_FP16) |
|
Zen 4 architecture optimizations (AVX512_BF16, VNNI) |
|
Zen 3 architecture optimizations |
|
Zen 2 architecture optimizations |
|
Zen 1 architecture optimizations |
|
AVX-512 instruction set |
|
AVX-512 using 256-bit YMM registers (f32 only) |
|
AVX2 instruction set |
|
AVX instruction set |
|
SSE 4.2 instruction set |
|
SSE 4.1 instruction set |
|
SSE 4a instruction set |
|
Supplemental SSE3 instruction set |
|
SSE3 instruction set |
|
SSE2 instruction set |
Note
avx512_ymm is only applicable for float32 (f32) datatypes. It forces the use of
256-bit YMM registers on AVX512-capable architectures, which can be beneficial in
certain scenarios. Other datatypes (bf16, int8) use the default AVX512 implementation
regardless of this setting.
Optimization Strategies:
Choose Appropriate Data Types: Use lower precision (bf16, int8) when accuracy permits
Enable Matrix Reordering: Reorder frequently used matrices for better cache performance
Utilize Post-Operations: Fuse operations to reduce memory bandwidth
Minimize Operations: Use matrix reordering beforehand so that DLP has to do fewer operations
Align Memory: Ensure proper memory alignment for vector instructions