Predefined Core PMC Events - Predefined Core PMC Events - 57368

CPU clock cycles not halted

The number of CPU cycles when the thread is not in halt state.

Retired Instructions

The number of instructions retired from execution. This count includes exceptions and interrupts. Each exception or interrupt is counted as one instruction.

Retired Macro Operations

The number of macro-ops retired. This count includes all processor activity - instructions, exceptions, interrupts, microcode assists, and so on.

Retired Branch Instructions

The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts

Retired Branch Instructions Mispredicted

The number of retired branch instructions that were mis-predicted.

Retired SSE/AVX Flops

The number of retired SSE/AVX flops. The number of events logged per cycle can vary from 0 to 64. This is a large increment per cycle event as it can count more than 15 events per cycle. This count both single precision and double precision FP events.

All Data cache accesses

The number of load and store ops dispatched to LS unit. This counts the dispatch of single op that performs a memory load, dispatch of single op that performs a memory store, dispatch of a single op that performs a load from and store to the same memory address.

L2cache access from L1 IC miss

TheL2 cache access requests due to L1 instruction cache misses.

L2cache access from L1 DC miss

TheL2 cache access requests due to L1 data cache misses. This also counts hardware and software prefetches.

L2cache miss from L1 IC miss

Counts all the Instruction cache fill requests that misses in L2 cache

L2cache miss from L1 DC miss

Counts all the Data cache fill requests that misses in L2 cache

L2Prefetcher Hits in L3

Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.

L2Prefetcher Misses in L3

Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches

L2cache hit from L1 IC miss

Counts all the Instruction cache fill requests that hits in L2 cache.

L2cache hit from L1 DC miss

Counts all the Data cache fill requests that hits in L2 cache.

L1demand DC fills from L2

The demand Data Cache (DC) fills from local L2 cache to the core.

L1demand DC fills from local CCX

The demand Data Cache (DC) fills from same the cache of same CCX or cache of different CCX in the same package (node).

L1demand DC fills from local Memory The demand Data Cache (DC) fills from

DRAM or IO connected in the same package

(node).

L1_DEMAND_DC_REFILLS_REMOTE

_CACHE

L1demand DC fills from remote cache

The demand Data Cache (DC) fills from cache of CCX in the different package (node).

L1_DEMAND_DC_REFILLS_REMOTE

_DRAM

L1demand DC fills from remote Memory The demand Data Cache (DC) fills from DRAM or IO connected in the different

package(node).

L1TLB miss L2 TLB hit

The instruction fetches that misses in the L1 Instruction Translation Lookaside Buffer (ITLB) but hit in the L2-ITLB.

L1TLB miss L2 TLB miss

The ITLB reloads originating from page table walker. The table walk requests are made for L1-ITLB miss and L2-ITLB misses.

L1DTLB miss

The L1 Data Translation Lookaside Buffer (DTLB) misses from load store micro-ops. This event counts both L2-DTLB hit and L2- DTLB miss.

L1DTLB miss

TheL2 Data Translation Lookaside Buffer (DTLB) missed from load store micro-ops.

Misaligned Loads

Thenumber of misaligned loads.

Ineffective Software Prefetches

The number of software prefetches that did not fetch data outside of the processor core. This event counts the Software PREFETCH instruction that saw a match on an already - allocated miss request buffer. Also counts the Software PREFETCH instruction that saw a DC hit.

CPU clock cycles not halted

The number of CPU cycles when the thread is not in halt state.

Retired Instructions

The number of instructions retired from execution. This count includes exceptions and interrupts. Each exception or interrupt is counted as one instruction.

Retired Macro Operations

The number of macro-ops retired. This count includes all processor activity - instructions, exceptions, interrupts, microcode assists, and so on.

Retired Branch Instructions

The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts

Retired Branch Instructions Mis-predicted

The number of retired branch instructions, that were mis-predicted. Note that only EX direct mis-predicts and indirect target mis-predicts are counted.

Retired SSE/AVX Flops

The number of retired SSE/AVX flops. The number of events logged per cycle can vary from0 to 64. This is large increment per cycle event, since it can count more than 15 events per cycle. This count both single precision and double precision FP events.

All Data cache accesses

The number of load and store ops dispatched to LS unit. This counts the dispatch of single op that performs a memory load, dispatch of single op that performs a memory store, and dispatch of a single op that performs a load from and store to the same memory address.

L2cache access from L1 IC miss

TheL2 cache access requests due to L1 instruction cache misses.

L2cache access from L1 DC miss

TheL2 cache access requests due to L1 data cache misses. This also counts hardware and software prefetches.

L2cache miss from L1 IC miss

Countsall the Instruction cache fill requests that misses in L2 cache.

L2cache miss from L1 DC miss

Counts all the Data cache fill requests that misses in L2 cache.

L2Prefetcher Hits in L3

Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.

L2Prefetcher Misses in L3

Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.

L2cache hit from L1 IC miss

Counts all the Instruction cache fill requests that hits in L2 cache.

L2cache hit from L1 DC miss

Counts all the Data cache fill requests that hits in L2 cache.

L1demand DC fills from L2

The demand Data Cache (DC) fills from local L2 cache to the core.

L1demand DC fills from local CCX

The demand Data Cache (DC) fills from the L3 cache or L2 in the same CCX.

L1demand DC fills from local Memory The demand Data Cache (DC) fills from

DRAM or IO connected in the same package

(node).

L1demand DC fills from remote external cache

The demand Data Cache (DC) fills from cache of CCX in the different package (node).

L1_DEMAND_DC_REFILLS_REMOTE

_DRAM

L1demand DC fills from remote Memory The demand Data Cache (DC) fills from DRAM or IO connected in the different

package(node).

L1demand DC fills from external caches

The demand Data Cache (DC) fills from cache of different CCX in the same or different package (node).

L1DC fills from local L2

The Data Cache (DC) fills from local L2 cache to the core.

L1DC fills from local CCX cache

The Data Cache (DC) fills from different L2 cache in the same CCX or L3 cache that belongs to the same CCX.

L1DC fills from local Memory

The Data Cache (DC) fills from DRAM or IO connected in the same package (node).

L1DC fills from remote Memory

The Data Cache (DC) fills from DRAM or IO connected in the different package (node).

L1 DC fills from local external CCX caches The Data Cache (DC) fills from cache of different CCX in the same or different package

(node).

L1DC fills from local Memory

The Data Cache (DC) fills from DRAM or IO connected in the same or different package (node).

L1DC fills from remote node

The Data Cache (DC) fills from cache of CCX in the different package (node) or the DRAM / IO connected in the different package (node).

L1_DC_REFILLS_LOCAL_CACHE_L2

_L3

L1DC fills from same CCX

The Data Cache (DC) fills from local L2 cache to the core or different L2 cache in the same CCX or L3 cache that belongs to the same CCX

L1DC fills from all the data sources

The Data Cache fills from all the data sources

L1TLB miss L2 TLB hit

The instruction fetches that misses in the L1 Instruction Translation Lookaside Buffer (ITLB) but hit in the L2-ITLB.

L1TLB miss L2 TLB miss

The ITLB reloads originating from page table walker. The table walk requests are made for L1-ITLB miss and L2-ITLB misses.

L1DTLB miss

The L1 Data Translation Lookaside Buffer (DTLB) misses from load store micro-ops. This event counts both L2-DTLB hit and L2- DTLB miss

L1DTLB miss

TheL2 Data Translation Lookaside Buffer (DTLB) missed from load store micro-ops

The number of misaligned loads.

Ineffective Software Prefetches

The number of software prefetches that did not fetch data outside of the processor core. This event counts the Software PREFETCH instruction that saw a match on an already allocated miss request buffer. Also counts the Software PREFETCH instruction that saw a DC hit.

CPU clock cycles not halted

The number of CPU cycles when the thread is not in halt state.

Retired Instructions

The number of instructions retired from execution. This count includes exceptions and interrupts. Each exception or interrupt is counted as one instruction.

Retired Macro Operations

The number of macro-ops retired. This count includes all processor activity - instructions, exceptions, interrupts, microcode assists, and so on.

Retired Branch Instructions

The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts

Retired Branch Instructions Mis-predicted

The number of retired branch instructions, that were mis-predicted.

Retired SSE/AVX Flops

The number of retired SSE/AVX flops. The number of events logged per cycle can vary from 0 to 64. This is a large increment per cycle event as it can count more than 15 events per cycle. This counts both the single precision and double precision FP events.

All Data Cache Accesses

The number of load and store ops dispatched to the LS unit. This counts the dispatch of a single op that performs a:

• memory load
• memory store
• load from and store to the same memory address

L2cache access from L1 IC miss

TheL2 cache access requests due to the L1 instruction cache misses.

L2cache access from L1 DC miss

TheL2 cache access requests due to the L1 data cache misses. This also counts the hardware and software prefetches.

L2cache miss from L1 IC miss

Counts all the instruction cache fill request misses in the L2 cache.

L2cache miss from L1 DC miss

Counts all the data cache fill request misses in L2 cache.

L2Prefetcher Hits in L3

Counts all the L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.

L2Prefetcher Misses in L3

Counts all the L2 prefetches accepted by the L2pipeline which miss the L2 and L3 caches.

L2cache hit from L1 IC miss

Counts all the instruction cache fill requests that hit the L2 cache.

L2cache hit from L1 DC miss

Counts all the data cache fill requests that hit the L2 cache.

L2cache hit from L2 HW Prefetch

Counts all the L2 prefetches accepted by L2 pipeline which hit the L2 cache.

L1demand DC fills from L2

The demand Data Cache (DC) fills from the local L2 cache to the core.

L1demand DC fills from local CCX

The demand Data Cache (DC) fills from the L3 cache or L2 in the same CCX.

L1demand DC fills from remote external cache

The demand DC fills from the CCX cache in the different package (node).

L1_DEMAND_DC_REFILLS_REMOTE_DRAM

L1demand DC fills from external caches The demand DC fills from the cache of different CCX in the same or different package (node).

L1DC fills from local L2

The DC fills from the local L2 cache to the core.

L1DC fills from local CCX cache

The DC fills from different L2 cache in the same CCX or L3 cache that belongs to the same CCX.

L1DC fills from local Memory

The DC fills from DRAM or IO connected in the same package (node).

The DC fills from the cache of different CCX in the same package (node).

The DC fills from the CCX cache in the different package (node).

L1DC fills from remote Memory

The DC fills from DRAM or IO connected in the different package (node).

The DC fills from cache of different CCX in the same or different package (node).

L1DC fills from local Memory

The DC fills from DRAM or IO connected in the same or different package (node).

L1DC fills from remote node

The DC fills from the CCX cache in the different package (node) or the DRAM / IO connected in the different package (node).

L1_DC_REFILLS_LOCAL_CACHE_L2

_L3

L1DC fills from same CCX

The DC fills from the local L2 cache to the core or different L2 cache in the same CCX or L3 cache that belongs to the same CCX.

The DC fills from all the data sources

L1TLB miss L2 TLB hit

The instruction fetches that misses in the L1 Instruction Translation Lookaside Buffer (ITLB) but hit in the L2-ITLB.

L1TLB miss L2 TLB miss

The ITLB reloads originating from page table walker. The table walk requests are made for L1-ITLB miss and L2-ITLB misses.

L1DTLB miss

The L1 Data Translation Lookaside Buffer (DTLB) misses from load store micro-ops. This event counts both L2-DTLB hit and L2-DTLBmiss

L1DTLB miss

TheL2 Data Translation Lookaside Buffer (DTLB) missed from load store micro-ops

Thenumber of misaligned loads.

Ineffective Software Prefetches

The number of software prefetches that did not fetch data outside of the processor core. This event counts the Software PREFETCH instruction that saw a match on allocated miss request buffer. Also counts the Software PREFETCH instruction that saw a DC hit.