Overview - Overview - 57368

The System Analysis tool AMDuProfPcm helps the user track, analyze and understand performance metrics for AMD processors. Metrics are collected from hardware performance monitoring counters and operating system interfaces, and are represented graphically with timeseries plots, graphs or as CSV reports. Basic performance modelling with roofline plots is also supported.

PMC

Performance Monitoring Counters (PMC) are hardware resources capable of counting events occurring inside the processor. To count a specific event, a counter is configured or loaded with a unique value referred to as an event configuration.

PMC Types

Core PMC

Every logical core has a set of performance monitoring counters referred to as Core PMCs capable of counting events inside the core. For a list of all the supported events for Core PMCs, see the section Core Performance Monitor Counters in the Processor Programming Reference. (Go to the Developer Central webpage and search for PPR).

L3 PMC (Uncore)

Every L3 cache has a set of performance monitoring counters referred to as L3 PMCs capable of counting events inside the L3 cache. For a list of all the supported events for L3 PMCs, see the section L3 Cache PMC Events in the Processor Programming Reference. (Go to the Developer Central webpage and search for PPR).

Metrics listed under option -m such as l3 are based on L3 PMC events and are referred to as L3 metrics.

DF (Data Fabric) PMC (Uncore)

Every socket has a set of performance monitoring counters referred to as DF PMCs, capable of counting events inside the Data Fabric. For a list of all the supported events for DF PMCs, see the section Data Fabric Performance Monitor Events in the Processor Programming Reference. (Go to the Developer Central webpage and search for PPR).

Metrics listed under option -m such as memory, xgmi, pcie, dma, ccm_bw are based on DF PMC events and are referred to as DF metrics.

Multiplexing

Multiplexing is required when the number of events to be monitored exceeds the number of available PMCs. Event configurations are grouped together to ensure metrics, which are computed using multiple events, are valid. Each group is configured or loaded onto the PMCs at a time in a round robin fashion. Each group resides on the PMCs for a duration before being replaced by the next group. For the duration an event group does not reside on the PMCs (since PMCs are occupied by other groups), the counts for those events are extrapolated from the last known measurement or sample. Due to this, multiplexing usually introduces noise in the collected data.

Multiplexing Interval

The interval for which an event group resides on PMCs during multiplexing. Multiplexing interval can be set using -t option and should be kept as low as possible for data accuracy.

Logging Interval

The interval after which a sample, containing the count values of all the events to be monitored, is logged. Logging interval can be set with -I option. When multiplexing, the logging interval must be a multiple of the product of the multiplexing interval and the number of event groups. AMDuProfPcm will adjust the logging interval to the closest value specified by the user while ensuring this condition is met.

Data Collection and Reporting

AMDuProfPcm can collect profiling data in two modes:

• Perf Mode (Non root mode)
• MSR Mode (Root mode)

Perf Mode (Only available on Linux)

PMCs are managed by perf subsystem on Linux and AMDuProfPcm utilizes perf subsystem for accessing PMCs. Perf subsystem enables sharing of hardware resources (PMCs) which allows multiple instances of AMDuProfPcm and other profilers to run simultaneously. On Linux, it is the default mode of data collection.

Multiplexing interval in perf mode can be set by:

• Writing the value (in ms) to /sys/devices/cpu/ perf_event_mux_interval_ms for Core PMCs.
• Writing the value (in ms) to /sys/devices/amd_l3/perf_event_mux_interval_ms for L3 PMCs.
• Writing the value (in ms) to /sys/devices/amd_df/perf_event_mux_interval_ms for DF PMCs.

Availability of /sys/devices/amd_l3/perf_event_mux_interval_ms and /sys/devices/amd_l3/perf_event_mux_interval_ms depend on kernel version and amd_uncore module.

MSR Mode

PMC are accessed by directly configuring PMC MSRs. Root privileges are required for this mode. Older Linux kernels might not support data collection with L3 PMCs and DF PMCs with Perf mode. In such scenarios you can use MSR mode.

Linux

PMC MSRs are accessed via msr kernel module. Use the --msr option to select this mode for data collection.

Windows

PMC MSRs are accessed via ioctl call to AMDPowerProfiler driver and is the default mode for data collection.

FreeBSD

PMC MSRs are accessed with the cpuctl module and is the default mode for data collection.