IBS Derived Events - IBS Derived Events

AMD uProf translates the IBS information produced by the hardware into derived event sample counts that resemble EBP sample counts. All the IBS-derived events contain IBS in the event name and abbreviation. Although IBS-derived events and sample counts look similar to the EBP events and sample counts, the source and sampling basis for the IBS event information are different.

Arithmetic calculation should never be performed between IBS derived event sample counts and EBP event sample counts. It is not meaningful to directly compare the number of samples taken for events that represent the same hardware condition. For example, fewer IBS DC miss samples is not necessarily better than a larger quantity of EBP DC miss samples.

Following table shows the IBS fetch events:

Table 1. IBS Fetch Events
IBS Fetch Event	Description
AMD “Zen1”, “Zen2”, and “Zen3” Platforms
IBS_FETCH	The number of all the IBS fetch samples. This derived event counts the number of all the IBS fetch samples that were collected including IBS- killed fetch samples.
IBS_FETCH_COMPLETED	The number of completed IBS sampled fetches. A fetch is completed if the attempted fetch delivers instruction data to the instruction decoder. Although the instruction data was delivered, it may still not be used. For example, the instruction data may have been on the “wrong path” of an incorrectly predicted branch.
IBS_FETCH_ABORTED	The number of IBS sampled fetches that aborted. An attempted fetch is aborted if it did not complete and deliver instruction data to the decoder. An attempted fetch may abort at any point in the process of fetching instruction data. An abort may be due to a branch redirection as the result of a mispredicted branch. The number of IBS aborted fetch samples is a lower bound on the number of unsuccessful, speculative fetch activity. It is a lower bound as the instruction data delivered by completed fetches may not be used.
IBS_FETCH_L1_ITLB_HIT	The number of IBS attempted fetch samples where the fetch operation initially hit in the L1 ITLB (Instruction Translation Lookaside Buffer).
IBS_FETCH_L1_ITLB_MISS_L2_ITLB_HIT	The number of IBS attempted fetch samples where the fetch operation initially missed in the L1 ITLB and hit in the L2 ITLB.
IBS_FETCH_L1_ITLB_MISS_L2_ITLB_MISS	The number of IBS attempted fetch samples where the fetch operation initially missed in both the L1 ITLB and the L2 ITLB.
IBS_FETCH_L1_ITLB_4K_PAGE	The number of IBS attempted fetch samples where the fetch operation produced a valid physical address (that is, address translation completed successfully) and used a 4-KByte page entry in the L1 ITLB.
IBS_FETCH_L1_ITLB_2M_PAGE	The number of IBS attempted fetch samples where the fetch operation produced a valid physical address (that is, address translation completed successfully) and used a 2 MB page entry in the L1 ITLB.
IBS_FETCH_LAT	The total latency of all IBS attempted fetch samples. Divide the total IBS fetch latency by the number of IBS attempted fetch samples to obtain the average latency of the attempted fetches that were sampled.
IBS_FETCH_L2C_MISS	The instruction fetch missed in the L2 Cache.
IBS_FETCH_ITLB_REFILL_LAT	The number of cycles when the fetch engine is stalled for an ITLB reload for the sampled fetch. If there is no reload, the latency will be 0.
AMD “Zen4” and AMD “Zen5” Platforms
IBS_FETCH	Number of all the IBS fetch samples. This derived event counts the number of all the IBS fetch samples that were collected, including IBS- killed fetch samples.
IBS_FETCH_ATTEMPTED	The number of IBS sampled fetches that were not killed fetch attempts. This derived event measures the number of useful fetch attempts and does not include the number of IBS killed fetch samples. This event should be used to compute ratios such as the ratio of IBS fetch IC misses to attempted fetches. The number of attempted fetches should equal the sum of the number of completed fetches and the number of aborted fetches.
IBS_FETCH_COMPLETED	The number of IBS sampled fetches that completed. A fetch is completed if the attempted fetch delivers instruction data to the instruction decoder. Although the instruction data was delivered, it may still not be used (for example, the instruction data may have been on the wrong path of an incorrectly predicted branch.)
IBS_FETCH_ABORTED	The number of IBS sampled fetches that aborted. An attempted fetch is aborted if it does not complete and deliver instruction data to the decoder. An attempted fetch may abort at any point in the process of fetching instruction data. An abort may be due to a branch redirection as the result of a mispredicted branch. The number of IBS aborted fetch samples is a lower bound on the amount of unsuccessful, speculative fetch activity. It is a lower bound as the instruction data delivered by completed fetches may not be used.
IBS_FETCH_L1_ITLB_HIT	The number of IBS attempted fetch samples where the fetch operation initially hit in the L1 ITLB (Instruction Translation Lookaside Buffer).
IBS_FETCH_L1_ITLB_ MISS_L2_ITLB_HIT	The number of IBS attempted fetch samples where the fetch operation initially missed in the L1 ITLB and hit in the L2 ITLB.
IBS_FETCH_L1_ITLB_ MISS_L2_ITLB_MISS	The number of IBS attempted fetch samples where the fetch operation initially missed in both the L1 ITLB and the L2 ITLB.
IBS_FETCH_L1_IC_MISS	The number of IBS attempted fetch samples where the fetch operation initially missed in the IC (instruction cache).
IBS_FETCH_L1_IC_HIT	The number of IBS attempted fetch samples where the fetch operation initially hit in the IC.
IBS_FETCH_L1_ITLB_4K_PAGE	The number of IBS attempted fetch samples where the fetch operation produced a valid physical address (for example, address translation completed successfully) and used a 4 KB page entry in the L1 ITLB.
IBS_FETCH_L1_ITLB_2M_PAGE	The number of IBS attempted fetch samples where the fetch operation produced a valid physical address (for example, address translation completed successfully) and used a 2 MB page entry in the L1 ITLB.
IBS_FETCH_L1_ITLB_1G_PAGE	The number of IBS attempted fetch samples where the fetch operation produced a valid physical address (for example, address translation completed successfully) and used a 1 GB page entry in the L1 ITLB.
IBS_FETCH_LAT	The total latency of all IBS attempted fetch samples. Divide the total IBS fetch latency by the number of IBS attempted fetch samples to obtain the average latency of the attempted fetches that were sampled.
IBS_FETCH_L2_MISS	The instruction fetch missed in the L2 Cache.
IBS_FETCH_ITLB_REFILL_LAT	The number of cycles when the fetch engine is stalled for an ITLB reload for the sampled fetch. If there is no reload, the latency will be 0.
IBS_FETCH_OP_CACHE_MISS	The number of IBS attempted fetch samples where the Op Cache was notable to supply all the bytes for the tagged fetch.
IBS_FETCH_L3_MISS	The number of IBS attempted fetch samples where the instruction fetch missed in the L3 cache on the same CCX.

Here is a list of IBS fetch metrics.

Table 2. IBS Fetch Metrics
IBS Fetch Metric	Description
IBS_FETCH_L1_IC_MISS_RATE_%	Percentage of IBS fetch L1 instruction cache misses with respect to the total number of IBS fetch attempts.
IBS_FETCH_LAT_AVE	The average IBS fetch latency. Calculated by dividing the IBS fetch latency by the total number of IBS fetch attempts.
IBS_FETCH_L1_ITLB_MISS_ L2_ITLB_HIT_RATE_%	Percentage of IBS fetch L1 ITLB miss and L2 ITLB hits with respect to the total number of IBS fetch attempts.
IBS_FETCH_L1_ITLB_MISS_ L2_ITLB_MISS_RATE_%	Percentage of IBS fetch L1 and L2 ITLB misses with respect to the total number of IBS fetch attempts.

Here is a list of IBS op events.

Table 3. IBS Op Events
IBS Op Event	Description
AMD “Zen1”, “Zen2”, and “Zen3” Platforms
IBS_ALL_OPS	The number of all the IBS op samples collected. These op samples may be branch ops, resync ops, ops that perform load/store operations, or undifferentiated ops (for example, those ops that perform arithmetic operations, logical operations, and so on). IBS collects data for the retired ops. No data is collected for the ops that are aborted due to pipeline flushes and so on. Thus, all the sampled ops are architecturally significant and contribute to the successful execution of programs.
IBS_TAG_TO_RET or IBS_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all the IBS op samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_COMP_TO_RET or IBS_COMP_TO_RETIRE_CYCLES	The total number of completion-to-retire cycles across all the IBS op samples. The completion-to-retire time of an op is the number of cycles from when the op completed to when the op retired.
IBS_BR	The number of IBS retired branch op samples. A branch operation is a change in the program control flow and includes unconditional and conditional branches, subroutine calls, and subroutine returns. Branch ops are used to implement AMD64 branch semantics.
IBS_MISP_BR or IBS_BR_MISP	The number of IBS samples for retired branch operations that were mispredicted. This event should be used to compute the ratio of mispredicted branch operations to all the branch operations.
IBS_TAKEN_BR	The number of IBS samples for the retired branch operations that were taken branches.
IBS_MISP_TAKEN_BR or IBS_TAKEN_BR_MISP	The number of IBS samples for the retired branch operations that were mispredicted taken branches.
IBS_RET	The number of IBS retired branch op samples where the operation was a subroutine return. These samples are a subset of all the IBS retired branch op samples.
IBS_MISP_RET or IBS_RET_MISP	The number of IBS retired branch op samples where the operation was a mispredicted subroutine return. This event should be used to compute the ratio of the mispredicted returns to all the subroutine returns.
IBS_RESYNC	The number of IBS resync op samples. A resync op is only found in certain microcoded AMD64 instructions and causes a complete pipeline flush. Note: Not supported on Zen3 and later processors.
IBS_LOAD_STORE	The number of IBS op samples for ops that perform either a load and/or store operation. Each op may perform a load operation, a store operation, or both a load and store operation (each to the same address).
IBS_LOAD	The number of IBS op samples for ops that perform a load operation.
IBS_STORE	The number of IBS op samples for ops that perform a store operation.
IBS_L1_DTLB_HIT	The number of IBS op samples where either a load or store operation initially hit the L1 DTLB (data translation lookaside buffer).
IBS_DTLB_L1M_L2H	The number of IBS op samples where either a load or store operation initially missed in the L1 DTLB and hit the L2 DTLB.
IBS_DTLB_L1M_L2M	The number of IBS op samples where either a load or store operation initially missed in both the L1 DTLB and the L2 DTLB.
IBS_DC_MISS or IBS_L1_DC_MISS	The number of IBS op samples where either a load or store operation initially missed in the L1 DC.
IBS_DC_HIT or IBS_L1_DC_HIT	The number of IBS op samples where either a load or store operation initially hit the L1 DC.
IBS_MISALIGN_ACC or IBS_MISALIGN_ACCESS	The number of IBS op samples where either a load or store operation caused a misaligned access (for example, the load or store operation crossed a 256-bit boundary).
IBS_BANK_CONF_LOAD	The number of IBS op samples where either a load or store operation caused a bank conflict with a load operation. Note: Not supported on Zen3 and later processors.
IBS_BANK_CONF_STORE	The number of IBS op samples where either a load or store operation caused a bank conflict with a store operation. Note: Not supported on Zen3 and later processors.
IBS_FORWARDED	The number of IBS op samples where data for a load operation was forwarded from a store operation. Note: Not supported on Zen3 and later processors.
IBS_STLF_CANCELLED	The number of IBS op samples where data forwarding to a load operation from a store was canceled. Note: Not supported on Zen3 and later processors.
IBS_UC_MEM_ACC or IBS_UC_MEM_ACCESS	The number of IBS op samples where a load or store operation accessed uncacheable (UC) memory.
IBS_WC_MEM_ACC or IBS_WC_MEM_ACCESS	The number of IBS op samples where a load or store operation accessed write combining (WC) memory.
IBS_LOCKED_OP	The number of IBS op samples where a load or store operation was a locked operation.
IBS_MAB_HIT	The number of IBS op samples where a load or store operation hit an already allocated entry in the Miss Address Buffer (MAB).
IBS_L1_DTLB_4K	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address and a 4 KB page entry in the L1 DTLB was used for the address translation.
IBS_L1_DTLB_2M	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address and a 2 M page entry in the L1 DTLB was used for the address translation.
IBS_L1_DTLB_1G	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address and a 1 GB page entry in the L1 DTLB was used for the address translation.
IBS_L2_DTLB_4K	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address, hit the L2 DTLB, and used a 4 KB page entry for the address translation.
IBS_L2_DTLB_2M	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address, hit the L2 DTLB, and used a 2 MB page entry for the address translation
IBS_L2_DTLB_1G	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address, hit the L2 DTLB, and used a 1 GB page entry for address translation.
IBS_LD_L1_DC_MISS_LAT or IBS_DC_MISS_LAT	The total L1 DC miss load latency (in processor cycles) across all the IBS op samples that performed a load operation and missed in the data cache. The miss latency is the number of clock cycles from when the L1 data cache miss was detected to when data was delivered to the core.
IBS_LOAD_RESYNC	LoadResync. Note: Not supported on Zen3 and later processors.
IBS_NB_LOCAL	The number of IBS op samples where a load operation was serviced from the local processor. Northbridge IBS data is only valid for the load operations that miss in both the L1 data cache and the L2 data cache. If a load operation crosses a cache line boundary, he IBS data reflects the access to the lower cache line. Note: Not supported on Zen3 and later processors.
IBS_NB_REMOTE	The number of IBS op samples where a load operation was serviced from a remote processor. Note: Not supported on Zen3 and later processors.
IBS_NB_LOCAL_L3	The number of IBS op samples where a load operation was serviced by the local L3 cache. Note: Not supported on Zen3 and later processors.
IBS_NB_LOCAL_CACHE	The number of IBS op samples where a load operation was serviced by a cache (L1 or L2 data cache) belonging to a local core which is a sibling of the core making the memory request. Note: Not supported on Zen3 and later processors.
IBS_LD_LOCAL_PEER_CACHE_HIT	IBS Load data returned from local L3 hit or different L1/L2 of same CCX or L1/L2/L3 hit in other CCX of same node. Note: Only supported for Zen3 processors.
IBS_NB_REMOTE_CACHE or IBS_LD_RMT_CACHE_HIT	The number of IBS op samples where a load operation was serviced by a remote L1 data cache, L2 cache, or L3 cache after traversing one or more coherent Hyper Transport links.
IBS_NB_LOCAL_DRAM or IBS_LD_LOCAL_DRAM_HIT	The number of IBS op samples where a load operation was serviced by local system memory (local DRAM through the memory controller).
IBS_NB_REMOTE_DRAM or IBS_LD_RMT_DRAM_HIT	The number of IBS op samples where a load operation was serviced by the remote system memory (after traversing one or more coherent Hyper Transport links and through a remote memory controller).
IBS_NB_LOCAL_OTHER	The number of IBS op samples where a load operation was serviced from local MMIO, configuration or PCI space, or from the local APIC. Note: Not supported on Zen3 and later processors.
IBS_NB_REMOTE_OTHER	The number of IBS op samples where a load operation was serviced from remote MMIO, configuration, or PCI space. Note: Not supported on Zen3 and later processors.
IBS_NB_CACHE_MODIFIED	The number of IBS op samples where a load operation was serviced from local or remote cache, and the cache hit state was the Modified (M) state. Note: Not supported on Zen3 and later processors.
IBS_NB_CACHE_OWNED	The number of IBS op samples where a load operation was serviced from local or remote cache, and the cache hit state was the Owned (O) state. Note: Not supported on Zen3 and later processors.
IBS_NB_LOCAL_LAT	The total data cache miss latency (in processor cycles) for the load operations that were serviced by the local processor. Note: Not supported on Zen3 and later processors.
IBS_NB_REMOTE_LAT	The total data cache miss latency (in processor cycles) for the load operations that were serviced by a remote processor. Note: Not supported on Zen3 and later processors.
AMD “Zen4” and AMD “Zen5” Platforms
IBS_ALL_OPS	The number of all the IBS op samples that were collected. These samples may be branch ops, resync ops, ops that perform load/store operations, or undifferentiated ops. For example, the ops that perform arithmetic operations, logical operations, and so on. IBS collects data for retired ops. No data is collected for ops that are aborted due to pipeline flushes and so on. Thus, all sampled ops are architecturally significant and contribute to the successful program execution.
IBS_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all the IBS op samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_COMP_TO_RETIRE_CYCLES	The total number of completion-to-retire cycles across all the IBS op samples. The completion-to-retire time of an op is the number of cycles from when the op completed to when the op retired.
IBS_BR	The number of IBS retired branch op samples. A branch operation is a change in program control flow; includes unconditional and conditional branches, subroutine and subroutine returns. Branch ops are used to implement AMD64 branch semantics.
IBS_BR_MISP	The number of IBS samples for the retired branch operations that were mispredicted. This event should be used to compute the ratio of mispredicted branch operations to all branch operations.
IBS_TAKEN_BR	The number of IBS samples for retired branch operations that were taken branches.
IBS_TAKEN_BR_MISP	The number of IBS samples for the retired branch operations that were mispredicted taken branches.
IBS_RET	The number of IBS retired branch op samples where the operation was a subroutine return. These samples are a subset of all the IBS retired branch op samples.
IBS_RET_MISP	The number of IBS retired branch op samples where the operation was a mispredicted subroutine return. This event should be used to compute the ratio of the mispredicted returns to all the subroutine returns.
IBS_FUSED_INST_OP	Tagged operation was part of a fused instruction pair.
IBS_MICROCODE_OP	Tagged operation from microcode.
IBS_BR_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all IBS op branch samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_BR_MISP_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all branch mispredict instruction op samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_TAKEN_BR_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all branch taken op samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_RET_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all branch return op samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_BR_COMP_TO_RETIRE_CYCLES	The total number of completion-to-retire cycles across all IBS branch samples. The completion-to-retire time of an op is the number of cycles from when the op completed to when the op retired.
IBS_BR_MISP_COMP_TO_RETIRE_CYCLES	The total number of completion-to-retire cycles across all branch mispredict instruction op samples. The completion-to-retire time of an op is the number of cycles from when the op completed to when the op retired.
IBS_TAKEN_BR_COMP_TO_RETIRE_CYCLES	The total number of completion-to-retire cycles across all IBS taken samples. The completion-to-retire time of an op is the number of cycles from when the op completed to when the op retired.
IBS_RET_COMP_TO_RETIRE_CYCLES	IBS branch return op completion-to-retire cycles.
IBS_LOAD_STORE	The number of IBS op samples for the ops that perform either a load and/or store operation. Each op may perform a load/store operation or both a load and store operation (each to the same address).
IBS_LOAD	The number of IBS op samples for the ops that perform a load operation.
IBS_STORE	The number of IBS op samples for the ops that perform a store operation.
IBS_L1_DTLB_HIT	The number of IBS op samples where either a load or store operation initially hit in the L1 DTLB (data translation look aside buffer).
IBS_DTLB_L1M_L2H	The number of IBS op samples where either a load or store operation initially missed in the L1 DTLB and hit in the L2 DTLB.
IBS_DTLB_L1M_L2M	The number of IBS op samples where either a load or store operation initially missed in both the L1 DTLB and the L2 DTLB.
IBS_L1_DC_MISS	The number of IBS op samples where either a load or store operation initially missed in the L1 data cache (DC).
IBS_L1_DC_HIT	The number of IBS op samples where either a load or store operation initially hit in the L1 data cache (DC).
IBS_MISALIGN_ACCESS	The number of IBS op samples where either a load or store operation caused a misaligned access (that is, the load or store operation crossed a 64 byte boundary).
IBS_UC_MEM_ACCESS	The number of IBS op samples where a load or store operation accessed uncacheable (UC) memory.
IBS_WC_MEM_ACCESS	The number of IBS op samples where a load or store operation accessed write combining (WC) memory.
IBS_LOCKED_OP	The number of IBS op samples where a load or store operation was a locked operation.
IBS_MAB_HIT	The number of IBS op samples where a load or store operation hit an allocated entry in the Miss Address Buffer (MAB).
IBS_L1_DTLB_4K	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address and a 4 KB page entry in L1 DTLB was used for the address translation.
IBS_L1_DTLB_2M	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address and a 2 MB page entry in L1 DTLB was used for the address translation.
IBS_L1_DTLB_1G	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address and a 1 GB page entry in L1 DTLB was used for the address translation.
IBS_L2_DTLB_4K	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address, hit L2 DTLB, and used a 4 KB page entry for the address translation.
IBS_L2_DTLB_2M	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address, hit L2 DTLB, and used a 2 MB page entry for the address translation.
IBS_L2_DTLB_1G	The number of IBS op samples where a load or store operation produced a valid linear (virtual) address, hit L2 DTLB, and used a 1 GB page entry for the address translation.
IBS_LD_L1_DC_MISS_LAT	The total L1 DC miss load latency (in processor cycles) across all the IBS op samples that performed a load operation and missed in the data cache. The miss latency is the number of clock cycles from when the L1 data cache miss was detected to when data was delivered to the core.
IBS_ST_L1_DC_MISS	The number of IBS op samples where a store operation missed in L1 data cache.
IBS_ST_L1_DC_HIT	The number of IBS op samples where a store operation hit in L1 data cache.
IBS_LD_L1_DC_HIT	The number of IBS op samples where a load operation hit in L1 data cache.
IBS_LD_L1_DC_MISS	The number of IBS op samples where a load operation missed in data cache.
IBS_LD_L2_HIT	The number of IBS op samples where a load operation hit in L2 cache.
IBS_LD_L2_MISS	The number of IBS op samples where a load operation missed in L2 Cache.
IBS_LD_L2_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the L2 cache.
IBS_L1_DTLB_REFILL_LAT	The number of cycles from when a L1 DTLB refill is triggered by a tagged op to when the L1 DTLB fill has been completed.
IBS_LD_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all IBS op load samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_ST_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all IBS op store samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_LD_ST_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all IBS op load and store samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_UC_MEM_ACCESS_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all IBS UC memory access op samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_WC_MEM_ACCESS_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all IBS WC memory access op samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_MISALIGN_ACCESS_TAG_TO_RETIRE_CYCLES	The total number of tag-to-retire cycles across all IBS misalign access op samples. The tag-to-retire time of an op is the number of cycles from when the op was tagged (selected for sampling) to when the op retired.
IBS_LD_RMT_CACHE_HIT	The number of IBS op samples where a load operation was serviced by a remote L1 data, L2, or L3 cache after traversing one or more coherent HyperTransport links.
IBS_LD_LOCAL_DRAM_HIT	The number of IBS op samples where a load operation was serviced by local system memory (local DRAM through the memory controller).
IBS_LD_RMT_DRAM_HIT	The number of IBS op samples where a load operation was serviced by the remote system memory (after traversing one or more coherent HyperTransport links and through a remote memory controller).
IBS_LD_LOCAL_CACHE_HIT	The number of IBS op samples where a load operation was serviced by the shared L3 cache or other L1/L2 cache in the same CCX.
IBS_LD_PEER_CACHE_HIT	The number of IBS op samples where a load operation was serviced by L2/L3 cache in a different CCX of same NUMA node.
IBS_LD_DRAM_HIT	The number of IBS op samples where a load operation was serviced by the DRAM.
IBS_LD_NVDIMM_HIT	The number of IBS op samples where a load operation was serviced by the NVDIMM.
IBS_LD_NON_MAIN_MEM_HIT	The number of IBS op samples where a load operation was serviced from MMIO, configuration or PCI space, or from the local APIC.
IBS_LD_EXT_MEM_HIT	The number of IBS op samples where a load operation was serviced by Extension memory.
IBS_LD_PEER_AGENT_MEM	The number of IBS op samples where a load operation was serviced by Peer agent memory.
IBS_LD_LOCAL_NVDIMM_HIT	The number of IBS op samples where a load operation was serviced by local long-latency DIMM.
IBS_LD_RMT_NVDIMM_HIT	The number of IBS op samples where a load operation was serviced by remote long-latency DIMM.
IBS_LD_CACHE_HITM	The number of IBS op samples where a load operation was serviced from the local or remote cache, and the cache hit state was the Modified (M) state.
IBS_LD_CACHE_HIT	The number of IBS op samples where a load operation was serviced from the local or remote cache, and the cache hit state was the Owned (O) state.
IBS_LD_LOCAL_CACHE_HITM	The number of IBS op samples where a load operation was serviced from local L3 or other L2 in the same CCX, and the cache hit state was the Modified (M) state.
IBS_LD_PEER_CACHE_HITM	The number of IBS op samples where a load operation was serviced from another L3 in same NUMA node, and the cache hit state was the Modified (M) state.
IBS_LD_RMT_CACHE_HITM	The number of IBS op samples where a load operation was serviced from another L3 in different NUMA node, and the cache hit state was the Modified (M) state.
IBS_LD_LOCAL_CACHE_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the shared L3 cache or other L1/L2 in the same CCX.
IBS_LD_PEER_CACHE_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the L2/L3 cache in different CCX of the same NUMA node.
IBS_LD_RMT_CACHE_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by L2/L3 cache in different CCX on different NUMA node.
IBS_LD_LOCAL_DRAM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the DRAM in same NUMA node.
IBS_LD_RMT_DRAM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the DRAM in different NUMA node.
IBS_LD_DRAM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the DRAM.
IBS_LD_NVDIMM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the NVDIMM-P.
IBS_LD_LOCAL_NVDIMM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the local NVDIMM.
IBS_LD_RMT_NVDIMM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the remote NVDIMM.
IBS_LD_EXTN_MEM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the extension memory.
IBS_LD_LOCAL_EXTN_MEM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the local extension memory.
IBS_LD_RMT_EXTN_MEM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the remote extension memory.
IBS_LD_PEER_AGENT_MEM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the peer agent memory.
IBS_LD_LOCAL_PEER_AGENT_MEM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the local peer agent memory.
IBS_LD_RMT_PEER_AGENT_MEM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the remote peer agent memory.
IBS_LD_NON_MAIN_MEM_HIT_LAT	The total latency (in processor cycles) for load operations that were serviced by the MMIO/Config/PCI/APIC.

Here is a list of IBS op metrics for AMD “Zen3”, “Zen4” and AMD “Zen5” platforms.

Table 4. IBS Op Metrics for AMD “Zen3”, “Zen4” and AMD “Zen5” Platforms
IBS Op Metric	Description
%IBS_BR	Percentage of IBS Branch operations with respect to the total IBS operations.
%IBS_BR_MISP	Percentage of IBS Branch mispredict operations with respect to IBS branch operations.
%IBS_TAKEN_BR	Percentage of IBS Branch taken operations with respect to IBS branch operations.
%IBS_RET	Percentage of IBS Branch return operations with respect to IBS branch operations.
%IBS_BR_TAG_TO_RETIRE_CYCLES	Percentage of IBS Branch op tag to retire cycles.
%IBS_BR_MISP_TAG_TO_RETIRE_CYCLES	Percentage of IBS Branch mispredict op tag to retire cycles.
%IBS_TAKEN_BR_TAG_TO_RETIRE_CYCLES	Percentage of IBS Branch taken op tag to retire cycles.
%IBS_RET_TAG_TO_RETIRE_CYCLES	Percentage of IBS Branch return op tag to retire cycles.
%IBS_BR_COMP_TO_RETIRE_CYCLES	Percentage of IBS Branch op completion to retire cycles.
%IBS_BR_MISP_COMP_TO_RETIRE_CYCLES	Percentage of IBS Branch mispredict op completion to retire cycles.
%IBS_TAKEN_BR_COMP_TO_RETIRE_CYCLES	Percentage of IBS Branch taken op completion to retire cycles.
%IBS_RET_COMP_TO_RETIRE_CY CLES	Percentage of IBS Branch return op completion to retire cycles.
IBS_BR_MISP_PTI	Number of Branch mispredicts per thousand operations. The number of branch mispredicts divided by the total number of branch operations, expressed as Per-Thousand-Instructions.
IBS_BR_MISP_RATE_%	Branch mispredict rate in percentage. The number of branch mispredicts divided by the total number of branch operations, expressed as percentage.
%IBS_BR_MISP_CYCLES	Percentage of cycles wasted due to branch mispredicts. The Tag-To-Retire cycles of branch mispredicts divided by the total Tag-To-Retire cycles of all the operations, expressed as percentage.
%IBS_LOAD_STORE	Percentage of Load and Store operations. The total number of load and store operations divided by the number of IBS OP samples, expressed as percentage.
%IBS_LOAD	Percentage of Load operations. The total number of load operations divided by the number of IBS OP samples, expressed as percentage.
%IBS_STORE	Percentage of Store operations. The total number of store operations divided by the number of IBS OP samples, expressed as percentage.
%IBS_L1_DTLB_REFILL_LAT_CYCLES	Percentage of cycles wasted due to L1 DTLB misses. The number of L1DTLB refill latency cycles divided by the total number of Tag-To-Retire cycles of all the operations, expressed as percentage.
IBS_ST_L1_DC_MISS_RATE_%	StoreL1 DC Miss rate in percentage. The number of store L1 DC misses divided by the total number of store ops, expressed as percentage.
IBS_LD_L1_DC_MISS_RATE_%	LoadL1 DC Miss rate in percentage. The number of load L1 DC misses divided by the total number of load ops, expressed as percentage.
IBS_LD_L1_DC_HIT_RATE_%	Load L1 DC Hit rate in percentage. The number of loadL1 DC hits divided by the total number of load ops, expressed as percentage.
IBS_LD_L2_HIT_RATE_%	LoadL2 Hit rate in percentage. The number of load L2 hits divided by the total number of load ops, expressed as percentage.
IBS_LD_LOCAL_CACHE_HIT_RATE_%	Percentage of load samples where the load operation was serviced by the shared L3 cache or other L1/L2 cache in the same CCX. The number of IBS_LD_LOCAL_CACHE_HIT divided by IBS_LOAD, expressed in percentage.
IBS_LD_PEER_CACHE_HIT_RATE_%	Percentage of load samples where the load operation was serviced by L2/L3 cache in a different CCX of same NUMA node. The number of IBS_LD_PEER_CACHE_HIT divided by IBS_LOAD, expressed in percentage.
IBS_LD_RMT_CACHE_HIT_RATE_%	Percentage of load samples where the load operation was serviced by L2/L3 cache of different CCX in different NUMA node. The number of IBS_LD_RMT_CACHE_HIT divided by IBS_LOAD, expressed in percentage.
IBS_LD_LOCAL_DRAM_HIT_RATE_%	Percentage of load samples where the load operation was serviced by local system memory (local DRAM via the memory controller) of same NUMA node. The number of IBS_LD_LOCAL_DRAM_HIT divided by IBS_LOAD, expressed in percentage.
IBS_LD_RMT_DRAM_HIT_RATE_%	Percentage of load samples where the load operation was serviced by DRAM in different NUMA node. The number of IBS_LD_RMT_DRAM_HIT divided by IBS_LOAD,expressed in percentage.
IBS_LD_DRAM_HIT_RATE_%	Percentage of load samples where the load operation was serviced by DRAM in the system. The number of IBS_LD_DRAM_HIT divided by IBS_LOAD, expressed in percentage.
IBS_LD_NVDIMM_HIT_RATE_%	Percentage of load samples where the load operation was serviced by NVDIMM in the system. The number of IBS_LD_NVDIMM_HIT divided by IBS_LOAD, expressed in percentage.
IBS_LD_EXT_MEM_HIT_RATE_%	Percentage of load samples where the load operation was serviced by Extension Memory in the system. The number of IBS_LD_EXT_MEM_HIT divided by IBS_LOAD, expressed in percentage. Note: Not supported on Zen3 processors
IBS_LD_PEER_AGENT_MEM_RATE_%	Percentage of load samples where the load operation was serviced by Peer agent Memory in the system. The number of IBS_LD_EXT_MEM_HIT divided by IBS_LOAD, expressed in percentage.
IBS_LD_NON_MAIN_MEM_HIT_R ATE_%	Percentage of load samples where the load operation was serviced from MMIO, configuration or PCI space, or from the local APIC in the system. The number of IBS_LD_NON_MAIN_MEM_HIT divided by IBS_LOAD, expressed in percentage.
IBS_LD_L1_DC_MISS_LAT_AVE	Average Load L1 DC Miss latency cycles. The number of load L1 DC misses latency divided by the total number of load L1 DC misses latency cycles.
%IBS_LD_L1_DC_MISS_LAT_CYCLES	Percentage of cycles wasted to fetch the data. The number of Load L1 DC misses latency cycles divided by the total number of Tag-To-Retire cycles of all the operations, expressed as percentage.
%IBS_LD_L2_HIT_LAT	Percentage of IBS load L2 hit latency cycles with respect to load L1 DC miss latency cycles.
%IBS_LD_LOCAL_CACHE_HIT_LAT	Percentage of IBS load local cache hit latency cycles with respect to the load L1 DC miss latency cycles.
%IBS_LD_PEER_CACHE_HIT_LAT	Percentage of IBS load peer cache hit latency cycles with respect to the load L1 DC miss latency cycles.
%IBS_LD_RMT_CACHE_HIT_LAT	Percentage of IBS load remote cache hit latency cycles with respect to the load L1 DC miss latency cycles.
%IBS_LD_LOCAL_DRAM_HIT_LAT	Percentage of IBS load local DRAM hit latency cycles with respect to the load L1 DC miss latency cycles.
%IBS_LD_RMT_DRAM_HIT_LAT	Percentage of IBS load remote DRAM hit latency cycles with respect to the load L1 DC miss latency cycles.
%IBS_LD_DRAM_HIT_LAT	Percentage of IBS load DRAM hit latency cycles with respect to the loadL1 DC miss latency cycles.
%IBS_LD_NVDIMM_HIT_LAT	Percentage of IBS load NVDIMM hit latency cycles with respect to the load L1 DC miss latency cycles.
%IBS_LD_EXTN_MEM_HIT_LAT	Percentage of IBS load Extension Memory hit latency cycles with respect to the load L1 DC miss latency cycles. Note: Not supported on Zen3 processors.
%IBS_LD_PEER_AGENT_MEM_HIT_LAT	Percentage of IBS load Peer Agent Memory hit latency cycles with respect to the load L1 DC miss latency cycles. Note: Not supported on Zen3 processors.
%IBS_LD_NON_MAIN_MEM_HIT_ LAT	Percentage of IBS load Non main memory hit latency cycles with respect to the load L1 DC miss latency cycles.

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