4.6.3. Performance Metrics for AMD EPYC™ Zen 4 and later Core Architecture Processors - 4.6.3. Performance Metrics for AMD EPYC™ Zen 4 and later Core Architecture Processors - 5.3 English - 57368

uProf User Guide (57368)
Document_ID
57368
Release_Date
2026-06-17
Version
5.3 English
Table 4.12 Performance Metrics for AMD EPYC™ Zen 4 and later Versions#

Metric Group

Metric Details

ipc

  • Utilization (%): Percentage of time the core was running, that is non-idle time.

  • System Time (%): Percentage of time in kernel mode.

  • User Time (%): Percentage of time in user mode.

  • System instruction (%):Percentage of retired instruction in kernel mode.

  • User instructions (%): Percentage of retired instructions in user mode.

  • Eff Freq: Core Effective Frequency (CEF) without halted cycles over the sampling period, reported in GHz. The metric is based on CEF = (APERF / TSC) * P0Freq. APERF is incremented in proportion to the actual number of core cycles while the core is in C6 state.

  • IPC (Sys + User): Instructions Per Cycle (IPC) is the average number of instructions retired per CPU cycle. This is measured using Core PMC events PMCx0C0 [Retired Instructions] and PMCx076 [CPU Clocks not Halted]. These PMC events are counted in both OS and User mode.

  • IPC (Sys): Instructions in kernel mode per cpu cycles in kernel mode. IPC of kernel mode.

  • IPC (User): Instructions in user mode per cpu cycles in user mode. IPC of user mode.

  • CPI (Sys + User): Cycles Per Instruction (CPI) is the multiplicative inverse of IPC metric. This is one of the basic performance metrics indicating how cache misses, branch mis-predictions, memory latencies, and other bottlenecks are affecting the execution of an application. A lower CPI value is better.

  • CPI (Sys): Cycles per Instructions for kernel mode.

  • CPI (User):Cycles per Instructions for user mode.

  • Giga Instructions Per Sec: The number of retired giga instructions per second

  • Locked Instructions (pti): The number of retired lock instructions in PTI.

  • Retired Branches (pti): The number of retired branch instructions in PTI.

  • Retired Branches Mispredicted (pti): The number of retired mis-predicted branch instructions in PTI.

fp

  • Retired SSE/AVX Flops (GFLOPs): The number of retired SSE/AVX FLOPs.

  • FP Dispatch Faults (PTI): The number of floating point instruction dispatch faults. This metric is in per thousand instructions (PTI).

avx_imix

  • Packed 512-bit FP Ops Retired (pto): The number of retired floating-point operations executed using packed 512-bit AVX-512 instructions. Each instruction operates on multiple elements in a 512-bit ZMM register (e.g., 8 doubles or 16 floats).

  • Packed 512-bit FP Ops Retired (%): Percentage of retired packed 512-bit floating-point operations out of all retired floating-point operations. Indicates the proportion of AVX-512 utilization.

  • Packed 256-bit FP Ops Retired (pto): The number of retired floating-point operations executed using packed 256-bit AVX instructions (e.g., AVX/AVX2). Each instruction operates on multiple elements in a 256-bit YMM register (e.g., 4 doubles or 8 floats).

  • Packed 256-bit FP Ops Retired (%): Percentage of retired packed 256-bit floating-point operations out of retired floating-point operations.

  • Packed 128-bit FP Ops Retired (pto): The number of retired floating-point operations executed using packed 128-bit SSE instructions. Each instruction operates on multiple elements in a 128-bit XMM register (e.g., 2 doubles or 4 floats).

  • Packed 128-bit FP Ops Retired (%): Percentage of retired packed 128-bit floating-point operations out of retired floating-point operations.

  • Scalar/MMX/x87 FP Ops Retired (%): Percentage of retired scalar floating-point operations, MMX instructions, and x87 floating-point instructions out of retired floating-point operations.

  • Scalar/MMX/x87-bit FP Ops Retired (pto): The number of retired scalar floating-point operations, MMX instructions, and x87 floating-point instructions. These are non-SIMD operations, typically less efficient than packed operations.

  • SSE/AVX Instructions Retired (pti):The number of retired SSE/AVX per thousand instructions.

  • MMX Instructions Retired (pti): The number of retired MMX per thousand instructions.

  • x87 Instructions Retired (pti): The number of retired x87 per thousand instructions.

l1

  • IC(32B) Fetch Miss Ratio: Instruction cache fetch miss ratio.

  • Op Cache Fetch Miss Ratio: Operation cache (64B) fetch miss ratio.

  • IC Access (PTI): All instruction cache accesses. This metric is in PTI.

  • IC Miss (PTI): Instruction cache Miss in PTI.

  • DC Access (PTI): All data cache (DC) accesses. This metric is in PTI.

dc

  • All Demand DC Fills (pti): Total number of data cache fills triggered by demand loads across all sources.

  • Demand DC Fills From Local L2 (pti): Data cache fills satisfied from the local L2 cache.

  • Demand DC Fills From Local L3 or different L2 in same CCX (pti): Fills served by the local L3 cache or another L2 within the same Core Complex (CCX).

  • Demand DC Fills From another CCX in same node (pti): Fills sourced from a different CCX within the same processor node.

  • Demand DC Fills From Local Memory or I/O (pti): Fills coming directly from local DRAM or I/O devices.

  • Demand DC Fills From another CCX in remote node (pti): Fills obtained from a CCX located in a remote node.

  • Demand DC Fills From Remote memory or I/O (pti): Fills fetched from remote DRAM or I/O resources.

  • All DC Fills (pti): Total number of data cache fills in PTI.

  • DC Fills From Same CCX (pti): Total number of data cache fills from the same CCX in PTI.

  • DC Fills From different CCX in same node (pti): Total number of data cache fills from different CCX in the same Numa node in PTI.

  • DC Fills From Local Memory (pti): Total number of data cache fills from local memory in PTI.

  • DC Fills From Remote CCX Cache (pti): Total number of data cache fills from CCX in the remote Numa node in PTI.

  • DC Fills From Remote Memory (pti): Total number of data cache fills from remote memory in PTI.

  • Remote DRAM Reads %: Percentage of data cache fills from remote memory out of total number of number of data cache fills.

l2

  • L2 Access: All the L2 cache accesses. This metric is in PTI.

  • L2 Access from IC Miss: The L2 cache accesses from IC miss. This metric is in PTI.

  • L2 Access from DC Miss: The L2 cache accesses from DC miss. This metric is in PTI.

  • L2 Access from HWPF: The L2 cache accesses from L2 hardware pre-fetching. This metric is in PTI.

  • L2 Miss: All the L2 cache misses. This metric is in PTI.

  • L2 Miss from IC Miss: The L2 cache misses from IC miss. This metric is in PTI.

  • L2 Miss from DC Miss: The L2 cache misses from DC miss. This metric is in PTI.

  • L2 Miss from HWPF: The L2 cache misses from L2 hardware pre-fetching. This metric is in PTI.

  • L2 Hit: All the L2 cache hits. This metric is in PTI.

  • L2 Hit from IC Miss: The L2 cache hits from IC miss. This metric is in PTI.

  • L2 Hit from DC Miss: The L2 cache hits from DC miss. This metric is in PTI.

  • L2 Hit from HWPF: The L2 cache hits from L2 hardware pre-fetching. This metric is in PTI.

tlb

  • L1 ITLB Miss: The instruction fetches the misses in the L1 Instruction Translation Lookaside Buffer (ITLB), but hit in the L2- ITLB plus the ITLB reloads originating from page table walker. The table walk requests are made for L1-ITLB miss and L2-ITLB misses. This metric is in PTI.

  • L2 ITLB Miss: The number of ITLB reloads from page table walker due to L1-ITLB and L2-ITLB misses. This metric is in PTI.

  • L1 DTLB Miss: The number of L1 Data Translation Lookaside Buffer (DTLB) misses from load store micro-ops. This event counts both L2-DTLB hit and L2-DTLB miss. This metric is in PTI.

  • L2 DTLB Miss: The number of L2 Data Translation Lookaside Buffer (DTLB)missed from load store micro-ops. This metric is in PTI.

  • All TLBs Flushed: All the TLBs flushed. This metric is in PTI.

l3

  • L3 Access: The count of L3 cache accesses.

  • L3 Hit %: Percentage of L3 Hit.

  • L3 Miss: The L3 cache miss.

  • L3 Miss (%): The L3 cache miss percentage.

  • Ave L3 Miss Latency: Average L3 miss latency in nanoseconds.

  • L3 Access (pti): The number of L3 cache accesses per thousand instructions.

  • L3 Miss (pti): The number of L3 cache misses per thousand instructions.

  • L3 Miss Latency From Local Memory or I/O (%): Percentage of L3 cache misses served by local DRAM or I/O, measured by latency contribution.

  • L3 Miss Latency From Remote Memory or I/O (%): Percentage of L3 cache miss latency caused by remote DRAM or I/O accesses.

  • L3 Miss Latency From another CCX in same node (%): Latency share from L3 misses resolved by a different CCX within the same node.

  • L3 Miss Latency From another CCX in remote node (%): Latency share from L3 misses resolved by a CCX in a remote node.

  • L3 Miss Latency From Local Extension Memory (CXL) (%): Percentage of latency from L3 misses served by local CXL-attached memory.

  • L3 Miss Latency From Remote Extension Memory (CXL) (%): Percentage of latency from L3 misses served by remote CXL-attached memory.

Memory

  • Total Memory Bw (GB/s): Total read and write memory bandwidth.

DRAM read and write data bytes for a local processor

  • Local DRAM Read Data Bytes (GB/s)

  • Local DRAM Write Data Bytes (GB/s)

DRAM read and write data bytes for a remote processor

  • Remote DRAM Read Data Bytes (GB/s)

  • Remote DRAM Write Data Bytes (GB/s)

Memory Read and Write bandwidth in GB/s for all the channels

  • Mem Ch-A RdBw (GB/s)

  • Mem Ch-A WrBw (GB/s)

ccm_bw

  • Local Inbound Read Data Bytes(GB/s): Local inbound data bytes to the CPU, for example, read data.

  • Local Outbound Write Data Bytes (GB/s): Local outbound data bytes from the CPU, for example, write data.

  • Remote Inbound Read Data Bytes(GB/s): Remote socket inbound data bytes to the CPU, for example, read data.

  • Remote Outbound Write Data Bytes (GB/s): Remote socket outbound data bytes from the CPU for example, write data.

Reports data traffic to CCM at interfaces 0 and 1

  • Local Socket Inbound Data to CPU Moderator (CCM) 0 at Interface 0 (GB/s)

  • Local Socket Outbound Data from CPU Moderator (CCM) 0 at Interface 0 (GB/s)

  • Remote Socket Inbound Data to CPU Moderator (CCM) 0 at Interface 0 (GB/s)

  • Remote Socket Outbound Data from CPU Moderator (CCM) 0 at Interface 0 (GB/s)

xgmi

xGMI Outbound Data Bytes (GB/s): Total outbound data bytes in Gigabytes per second.

dma (not available in AMD Zen 1, AMD Zen 2, and AMD Zen 3 processors)

  • Total Upstream DMA Read Write Data Bytes (GB/s): Total upstream DMA including read and write.

  • I/O read data bytes to local processor: Local upstream DMA read data bytes.

  • I/O write data bytes to local processor: Local upstream DMA write data bytes.

  • I/O read data bytes to remote processor: Remote socket upstream DMA read data bytes.

  • I/O write data bytes to remote processor: Remote socket upstream DMA write data bytes.

pcie

Approximate PCIe bandwidth in GB/s

  • PCIe0 (GB/s)

  • PCIe1 (GB/s)

  • PCIe2 (GB/s)

  • PCIe3 (GB/s)

PCIe bandwidth for read and write transactions, local, and remote node bandwidth. Per quad PCIe bandwidth

  • Total PCIE Bandwidth (GB/s)

  • Total PCIE Rd Bandwidth (GB/s)

  • Total PCIE Wr Bandwidth (GB/s)

  • Total PCIE Bandwidth Local (GB/s)

  • Total PCIE Bandwidth Remote (GB/s)

  • Total PCIE Rd Bandwidth Local (GB/s)

  • Total PCIE Wr Bandwidth Local (GB/s)

  • Total PCIE Rd Bandwidth Remote (GB/s)

  • Total PCIE Wr Bandwidth Remote (GB/s)

  • Quad 0 PCIE Rd Bandwidth Local (GB/s)

  • Quad 0 PCIE Wr Bandwidth Local (GB/s)

  • Quad 0 PCIE Rd Bandwidth Remote (GB/s)

  • Quad 0 PCIE Wr Bandwidth Remote (GB/s)

  • Quad 1 PCIE Rd Bandwidth Local (GB/s)

  • Quad 1 PCIE Wr Bandwidth Local (GB/s)

  • Quad 1 PCIE Rd Bandwidth Remote (GB/s)

  • Quad 1 PCIE Wr Bandwidth Remote (GB/s)

  • Quad 2 PCIE Rd Bandwidth Local (GB/s)

  • Quad 2 PCIE Wr Bandwidth Local (GB/s)

  • Quad 2 PCIE Rd Bandwidth Remote (GB/s)

  • Quad 2 PCIE Wr Bandwidth Remote (GB/s)

  • Quad 3 PCIE Rd Bandwidth Local (GB/s)

  • Quad 3 PCIE Wr Bandwidth Local (GB/s)

  • Quad 3 PCIE Rd Bandwidth Remote (GB/s)

  • Quad 3 PCIE Wr Bandwidth Remote (GB/s)

swpfdc

Software prefetch data cache from various nodes and CCX

  • SwPfDC Fills from DRAM or IO connected in remote node (pti)

  • SwPfDC Fills from CCX Cache in remote node (pti)

  • SwPfDC Fills from DRAM or IO connected in local node (pti)

  • SwPfDC Fills from Cache of another CCX in local node (pti)

  • SwPfDC Fills from L3 or different L2 in same CCX (pti)

  • SwPfDC Fills from L2 (pti)

hwpfdc

Hardware prefetch data cache from various nodes and CCX

  • HwPfDC Fills from DRAM or IO connected in remote node (pti)

  • HwPfDC Fills from CCX Cache in remote node (pti)

  • HwPfDC Fills from DRAM or IO connected in local node (pti)

  • HwPfDC Fills from Cache of another CCX in local node (pti)

  • HwPfDC Fills from L3 or different L2 in same CCX (pti)

  • HwPfDC Fills From L2 (pti)

pipeline_util

  • Total_Dispatch_Slots: Up to 6 instructions can be dispatched in one cycle.

  • SMT_Disp_contention: Percentage of unused dispatch slots as other thread was selected.

  • Frontend_Bound: Percentage of dispatch slots that remained unused as the front end did not supply enough instructions/operations.

  • Bad_Speculation: Percentage of unused dispatch slots as other thread was selected.

  • Backend_Bound: Percentage of dispatch slots that remained unused because of the back end stalls.

  • Retiring: Percentage of dispatch slots used by the retired operations.

  • IPC: Instructions per cycle.

  • Frontend_Bound.Latency: Percentage of dispatch slots that remained unused because of a latency bottleneck in the front end, such as Instruction Cache or ITLB misses.

  • Frontend_Bound.BW: Percentage of dispatch slots that remained unused because of a bandwidth bottleneck in the front end, such as decode bandwidth or Op Cache fetch bandwidth.

  • Bad_Speculation.Mispredicts: Percentage of dispatched ops that were flushed due to branch mis-predicts.

  • Bad_Speculation.Pipeline_Restarts: Percentage of dispatched ops that were flushed due to the pipeline restarts (resyncs).

  • Backend_Bound.Memory: Percentage of dispatched slots that remained unused because of stalls due to the memory subsystem.

  • Backend_Bound.CPU: Percentage of dispatched slots that remained unused because of stalls not related to the memory subsystem.

  • Retiring.Fastpath: Percentage of dispatch slots used by the retired fastpath operations.

  • Retiring.Microcode: Percentage of dispatch slots used by the retired microcode operations.

UMC

Note

Supported only in Zen 5 servers.

  • Total Est Mem Bw (GB/s): Estimated total memory bandwidth usage, combining both reads and writes.

  • Total Est Mem RdBw (GB/s): Estimated memory bandwidth consumed by read operations.

  • Total CXL Write Memory BW (GB/s): Estimated memory bandwidth consumed by write operations.

CXL

Note

Supported only in Zen 5 servers.

  • Total Est Mem WrBw (GB/s): Overall memory bandwidth utilized through the CXL interface, including reads and writes.

  • Total CXL Read Memory BW (GB/s): Bandwidth consumed by memory read operations over CXL.

  • Total CXL Write Memory BW (GB/s): Bandwidth consumed by memory write operations over CXL.

Note

Memory channels are available with package level.