4.2. Performance Monitoring Counters (PMC) - 4.2. Performance Monitoring Counters (PMC) - 5.3 English - 57368

Performance Monitoring Counters (PMC) are hardware resources capable of counting events occurring inside the processor. To count a specific event, a counter is configured or loaded with a unique value referred to as an event configuration.

PMC is categorized as follows:

• Core PMC: Every logical core has a set of performance monitoring counters referred to as Core PMCs capable of counting events inside the core. For a list of all the supported events for Core PMCs, refer to Core Performance Monitor Counters in the Processor Programming Reference, and search for the specific PPR.

• L3 PMC (Uncore): Every L3 cache has a set of performance monitoring counters referred to as L3 PMCs capable of counting events inside the L3 cache. For a list of all the supported events for L3 PMCs, see the section L3 Cache PMC Events in the Processor Programming Reference, and search for the specific PPR. Metrics listed under option -m such as l3 are based on L3 PMC events and are referred to as L3 metrics.

• DF (Data Fabric) PMC (Uncore): Every socket has a set of performance monitoring counters referred to as DF PMCs, capable of counting events inside the Data Fabric. For a list of all the supported events for DF PMCs, see the section Data Fabric Performance Monitor Events in the Processor Programming Reference, and search for the specific PPR. Metrics listed under option -m such as memory, xgmi, pcie, dma, ccm_bw are based on DF PMC events and are referred to as DF metrics.