CPM4/CPM5, as master, generates all transactions with the same AXI ID.
With CPM4/CPM5 as Root Complex, when SMMU is enabled, ordering is not followed between different Shareable domain memories that have the same AXI ID.
This is a Vendor IP CCI-500 bug, where CCI cannot maintain shareable transaction with mixed cacheability such as Write-back with Device and Non-Cacheable.
Essentially, CCI does not enforce OWO (ORDERED_WRITE_OBSERVATION) ordering for the shareable writes going to different slaves, resulting in system level ordering failure.