Description - Description

000039996 - Design Advisory for AMD Spartan UltraScale+ FPGAs: SelectIO Internal Pull Ups Enabled Briefly During Initialization

Release Date
2026-05-20
Revision
1.0 English

During Spartan™ UltraScale+™ FPGA initialization (INIT_B = Low), SelectIO pins are expected to remain in a high-impedance state when PUDC_B = High.

On affected devices, when the SCAN_CLEAR_EN eFUSE is programmed and PUDC_B = High, the SelectIO internal weak pull-ups can briefly turn on for approximately 5-11 µs during initialization.

This brief pull-up condition can occur during the following events:

  • Power‑up reset initialization
  • PROGRAM_B or JPROG reset initialization
  • Secure lockdown initiated by a tamper event

Normal SelectIO behavior is restored after initialization; device operation after configuration is not affected.

Affected I/O types: HDIO, HPIO, and XP5IO.

Trigger condition: SCAN_CLEAR_EN eFUSE programmed and PUDC_B = High.

  • Scan clear is a feature required on applications that must verify the zeroization of all storage elements. For more details on the scan clear feature, refer to UG1721 available on the design security lounge.

 

Devices Impacted:

This advisory applies to the following Spartan UltraScale+ production devices:

SU10P, SU25P, SU35P, SU45P, SU60P, SU150P, SU200P

 

  • Impacted by default:
    • SU10P, SU25P, SU35P production devices with date codes earlier than 2618 because the SCAN_CLEAR_EN eFUSE is programmed by default on these devices.
  • Impacted if SCAN_CLEAR_EN  is programmed by the user:
    • All SU45P, SU60P, SU150P, SU200P production devices, and SU10P, SU25P, and SU35P production devices with date codes 2618 or later.
  • Not affected:
    • SU65P and SU100P