000039996 - Design Advisory for AMD Spartan UltraScale+ FPGAs: SelectIO Internal Pull Ups Enabled Briefly During Initialization - During Spartan™ UltraScale+™ FPGA initialization (INIT_B = Low), SelectIO pins are expected to remain in a high-impedance state when PUDC_B = High.
On affected devices, when the SCAN_CLEAR_EN eFUSE is programmed and PUDC_B = High, the SelectIO internal weak pull-ups can briefly turn on for approximately 5-11 µs during initialization.
- Release Date
- 2026-05-20
- Revision
- 1.0 English