This is a known issue in 2025.1.x and prior for the X5PLL. It is resolved in 2025.2.
Versal AI Edge Gen 2, Versal Prime Gen 2, Versal Premium Gen 2 and Versal RF have a minimum production speed file greater than 2025.2, consequentially design targeting these families need to migrate to their production speed file Vivado release where the issue is resolved.
If you are using the XCVM2152** in a Vivado version earlier than 2025.2 download the attached script to check if a problematic clocking topology is used in your design.
source ./check_x5pll_phase_jitter.v2.tcl -quiet
check_x5pll_phase_jitterIf no issues are found the script will report
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No X5PLL topology with missing phase jitter found
If the script finds an issue in the path it will report X5PLLs that have a timed path between them.
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Clock pair with potential missing X5PLL phase jitter: clk_out01 (X5PLL_X22Y0)-> clk_out12 (X5PLL_X23Y0)
If the design has a clock pair warning flagged the design you will need to rerun timing.
Download the patch attached to the Answer Record and rerun timing on the design.
For example
report_timing_summary -name retimeIf the design meets timing then no further action is required.
If the design no longer meets timing then appropriate action should be taken. Start with rerunning route_design to address the timing issue.