If a X5PLLs is used to create clocks and there is a path with a clock domain crossing to another Clock Modifying Block, MMCM, DPLL or X5PLL the timing of the path between the 2 clocks domains may under report due to the X5PLL_PHASE_JITTER not used correctly in the clock_uncertainty calculation.
Devices Impacted : XCVM2152**, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, Versal Premium Series Gen 2 and Versal RF Series