000039194 - Design Advisory Versal X5PLL : Timing of X5PLL may underreport jitter for some topologies - If a X5PLLs is used to create clocks and there is a path with a clock domain crossing to another Clock Modifying Block, MMCM, DPLL or X5PLL the timing of the path between the 2 clocks domains may under report due to the X5PLL_PHASE_JITTER not used correctly in the clock_uncertainty calculation.

Release Date

2026-01-28

Revision

1.0 English