000038581 - Versal MIPI C-PHY (P4/P6/P7 Triplet Group) in a single X5IO bank limitation causes “[Mig 66-441] Maximum number of XPLL’s available per bank is 2” during implementation - In all devices containing X5IO when instantiating multiple MIPI C-PHY RX IP lanes in the upper Triplets (P4/P6/P7) will encounter errors during implementation.

Release Date

2025-10-02

Revision

1.0 English