Solution - Solution

000037870 - Versal Prime XCVM2152 - Missing timing arcs and MIPI IP patches

Release Date
2025-09-11
Revision
1.0 English

The minimum supported Vivado production version for XCVM2152 is 2025.1 with the patch.

This patch consists of three components, and all must be included in the XILINX_PATH environment variable. 

For example:

setenv XILINX_PATH /AR000037870_vivado_2025_1_preliminary_rev1/vivado:/AR000038390_Vivado_2025_1_preliminary_rev1/vivado:/AR000037870_shareddata_2025_1_preliminary_rev1/shareddata 

 

When the patch is applied correctly, Vivado will display the corresponding patch numbers upon GUI launch.

There are a Known Issues after the patch is applied.

MIPI CPHY RX:

MIPI CPHY RX has slack violations due to fifo_wrclk constraints regenerated at the opt_design stage. To resolve this, add the following two constraints at the design top level XDC in the Vivado project:

 

set_false_path -through  [get_cells -hierarchical -filter {NAME =~ *rx_phy_crx_fabric_top/crx_hsalp_inst*/MIPI_LIB_FIFO.symbuf/aclk_dpram*/RAM*}]

set_false_path -through [get_pins -hierarchical  -filter {NAME =~ *rx_phy_crx_fabric_top/crx_hsalp_inst*/MIPI_LIB_FIFO.symbuf/aclk_wp_reg*/CLR*}]

 

 

Note:

(a) Please refer to 000037289 - MIPI D-PHY RX and MIPI C-PHY RX Pin Assignment Guidelines for Devices with X5IO Banks

(b) This patch includes the fix for 000036582 - Patched Version of 2025.1 causes Locked IPs, so no separate action is required.
(c) Please refer to the guidance in 11630 - Install - How do I check or manually set environment variables?