The XCVM2152 device speed files have three Known Issues in the 2025.1 and 2024.2.x releases:
- When using Octads 4,6,7 with the FIFO_WR_CLK used for the FIFO_RD_CLK which is used in MIPI, there are timing issues with the FIFO_WR_CLK which results in Critical Warnings in 2025.1. See 000037688 - 2024.2.1/2025.1 X5IO - MIPI CPHY issue with the timing for further details.
- When using the X5PLL Dynamic Reconfiguration or Phase shifting, some paths might not be timed correctly. See 000037786 - 2024.2.x/2025.1, Versal - Issues with the timing of X5PLL port for further details.
- MIPI C-PHY IP with multi-lanes (or multi-trios) configuration is not supported.