Version Found: 2024.2
Version Resolved: 2025.1 - See (Answer Record 75764)
The VREF_CA is incorrectly programmed at data rates of 2400Mbps and above for LPDDR4 and LPDDR4X devices, when both channels of the DDRMC are enabled. This includes dual-channel 2x32 LPDDR4 and LPDDR4X interfaces, as well as 1x48 ECC operating modes. This is a new behavior introduced in Vivado 2024.2 and is resolved in Vivado 2025.1.
An error in the DDRMC MicroBlaze Microcode sets the VREF_CA MR12 value to 0x0 instead of the expected value determined by the memory type and topology.
This sets the VREF_CA value to the minimum of 10% of the reference voltage. This lowers the VREF_CA margin but does not necessarily cause all design to have operational issues. Some designs might not show any issues, while others might have problems in various calibration stages or post calibration data errors. This is dependent on the specific PCB layout and PDN quality of the design.