000037436 - Design Advisory for Versal Adaptive SoC DDRMC - Incorrect VREF_CA Programming for Certain LPDDR4 and LPDDR4X Topologies in Vivado 2024.2 - For certain Versal LPDDR4 and LPDDR4X topologies, the VREF_CA is incorrectly programmed at data rates of 2400Mbps and above when both channels of the DDRMC are enabled. This includes dual-channel 2x32 LPDDR4 and LPDDR4X interfaces, as well as 1x48 ECC operating modes.

Release Date

2025-05-02

Revision

1.0 English