Solution

000035682 - Design Advisory - Versal Adaptive SoC Integrated Block/DMA and Bridge Subsystem for PCI Express [Vivado 2024.1] - General guidance on easier timing closure, and specific guidance on accessing link configurations limited by the IP GUI

Release Date
2024-06-20
Revision
1.0 English

For Versal Adaptive SoC devices, PL PCIE based IP solutions include the integrated block for PCI Express, clocking, transceivers, logic, and block memory.  These IP solutions must achieve timing closure during design implementation, including user-contributed application logic.

General Guidance on Selecting Link Configurations and Placements for Easier Timing Closure

Given the multiple resources involved in these IP solutions, timing closure is easier if the resources are placed close to each other in the programmable logic array.  As a simple example, GT and PL PCIe must be located on the same side of the device, and their placement must exhibit some degree of adjacency to avoid significant routing jog in the connections between them which can complicate timing closure.

As another example, URAM and BRAM connected to the PL PCIE or incorporated in optional soft IP for DMA / Bridge, are best positioned near the PL PCIE and in the surrounding region of programmable logic.  This reduces routing distances, and in some cases routing congestion, both of which can complicate timing closure.  In support of easier timing closure on these paths and of soft logic in general, preferred selection of PL PCIE for high throughput applications (high link width, high link rate, or combination of both) will be in areas with a wide region of programmable logic, not impinged by programmable logic array borders nor by user-added placement directives on other logic.  The corollary to this is the potential advantage of adding placement directives on the IP solution to reserve resources near the PL PCIE.

AMD recommends the following preference order for use of integrated blocks for PCI Express:

  1. CPM, if available
  2. PL PCIE, if available in a large region of programmable logic
  3. PL PCIE, if available in a small region of programmable logic

This is illustrated in the following example of a generic device based on Versal Architecture:

 

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Note: as referenced by the title and description of this article, the IP customization GUI, by default, limits access to challenging link configurations and placements of PL PCIE based IP solutions, even though they are listed as supported. These link configurations and placements can be enabled via a Tcl command described in the next section of this article.

 

For information on a specific device, see the Die Level Bank Numbering and Device Diagrams section of the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013), or the Viewing Device Resources section of the Vivado Design Suite User Guide: I/O and Clock Planning (UG899) .  AMD recommends that users validate their design intent by running one of the available IP Example Designs available through Vivado Design Suite.

Specific Guidance on Accessing Link Configurations Limited by the IP Customization GUI

After reviewing this answer record, enable access-limited link configurations and placements with the following property setting via Tcl command:

set_property -dict [list CONFIG.all_speeds_all_sides {YES}] [get_ips pcie_versal_0]

AMD urges users setting this property to validate their design intent by running one of the available IP Example Designs available through Vivado Design Suite.  If timing closure is achievable with the IP Example Design, continue with the user design; otherwise seek support. 

For support, visit the Community Forums PCI Express topic area, or contact AMD Adaptive SoC & FPGA Support or your local field application engineer.  

For release notes and the latest status on known issues, see:

 

Revision History:

  • 10/26/2023 - Initial Release
  • 06/20/2024 - Updated for 2024.1