For Versal Adaptive SoC devices in -1L, -1M, and -2L grades, certain link configurations and placements can be challenging for timing closure, in addition to generally increased challenge for high performance DMA / Bridge soft IP solutions.
The IP customization GUI by default limits access to challenging link configurations and placements even though they are listed as supported in Versal Adaptive SoC Integrated Block for PCI Express Product Guide (PG343) and Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344).
The access limitations apply to the following PL PCIE based solutions in -1L, -1M, and -2L grades:
- Versal Adaptive SoC Integrated Block for PCI Express, for PL PCIE placement on the same side as the CPM
- Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express, for PL PCIE placement on all sides
AMD advises users to review this answer record at the start of project planning and prior to the start of board schematic capture.
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For more information on PCIe Debug, see https://xilinx.github.io/pcie-debug-kmap/pciedebug/build/html/index.html