AMD Vivado Hardware Manager and XSCT/XSDB JTAG tools, boards, and cables are NOT impacted by this device issue.
This issue does not affect typical third-party JTAG systems. However, the exceptional cases are listed below for review.
When an affected Versal device is the only device in a JTAG chain or is the last device in a JTAG chain of devices, there is typically NO impact. This is because the issue typically affects only the last output instruction capture bit, which is a don't-care status bit.
For general JTAG chain cases, this issue typically does NOT have any functional impact because downstream JTAG devices/cables normally capture TDO at the rising-edge of TCK, which is prior to the TDO change from this issue.
AMD CPLDs, FPGAs, and SoCs capture TDO at the rising-edge of TCK with a sufficiently small hold time requirement and thus are not affected by this issue when downstream from an affected device in a JTAG chain.
However, in the following exceptional cases, this issue can cause a downstream device/cable to capture an incorrect bit value during instruction shift operations:
- Non-AMD downstream devices with an unusually long TDI input hold time (> 3 ns) requirement
- Non-AMD JTAG cables that have advanced modes to capture TDO from an affected device at later phases of TCK.
If one of the exceptional cases results in an incorrect bit value captured from TDO, downstream devices might receive incorrect instruction opcodes or JTAG cables might receive incorrect instruction capture (status) values.
Note: AMD Vivado Hardware Manager and XSCT/XSDB JTAG tools, boards, and cables are NOT impacted by this device issue. AMD SOMs are typically not affected by this issue per the normal TDO capture protocol, but exceptional downstream TDO capture cases (listed above) can exist for the system in which the SOM is embedded.
Work-around(s):
- Use standard JTAG cable modes that capture TDO at the rising-edge of TCK. Disable advanced JTAG cable modes/tests that capture TDO at later phases of the TCK cycle. (AMD JTAG cables capture TDO at the rising-edge of TCK and are NOT affected by devices with this issue.)
- [For PCB design] Do not put devices with unusually long JTAG input hold time requirements (> 3 ns from rising-edge of TCK) after an affected device in the JTAG chain, or when necessary, extend board level delays of the TDO signal from affected devices to ensure that TDO output meets the required hold time of downstream devices or JTAG cables. (AMD CPLDs, FPGAs, and SoCs in a downstream JTAG chain position are not impacted by this issue because AMD devices have sufficiently small hold time requirements. AMD JTAG cables are not impacted by this issue.)
Configurations Affected:
The following devices based on SSI technology are affected by this issue:
- All Versal HBM devices: VH1522, VH1542, VH1582, VH1742, and VH1782.
- The following Versal Premium devices: VP1502, VP1552, VP1702, VP1802, VP1902, VP2502, and VP2802.