The JTAG test data output (TDO) has reduced hold time (less than the expected half TCK clock period) at exit from the shift instruction register (Shift-IR) state.
In affected devices based on stacked silicon interconnect (SSI) technology, the JTAG test data output (TDO) has reduced hold time at exit from the shift instruction register (Shift-IR) state. For the affected JTAG Shift-IR TDO output cycle, the TDO hold time is reduced from the expected half TCK clock period to 3 ns after the rising edge of the TCK clock.
During JTAG shift operations, each JTAG TDO output bit value is output after a falling-edge of TCK and is expected to be held until the next falling edge of TCK. In affected devices based on stacked silicon interconnect (SSI) technology and only at the exit of the shift instruction register (Shift-IR) state, the JTAG TDO output can change earlier than expected.
TDO can change after the rising-edge of TCK instead of the falling-edge of TCK. See the below figure.
Note: The shift data register (Shift-DR) operation is NOT affected by this issue.
This issue will not be fixed for the devices listed in the below Configurations Affected subsection.