000035627 - Design Advisory for Versal - JTAG TDO Has Reduced Hold Time At Exit From Shift-IR State - In affected devices based on stacked silicon interconnect (SSI) technology, the JTAG test data output (TDO) has reduced hold time at exit from the shift instruction register (Shift-IR) state. For the affected JTAG Shift-IR TDO output cycle, the TDO hold time is reduced from the expected half TCK clock period to 3 ns after the rising edge of the TCK clock. During JTAG shift operations, each JTAG TDO output bit value is output after a falling-edge of TCK and is expected to be held until the next falling edge of TCK. In affected devices based on stacked silicon interconnect (SSI) technology and only at the exit of the shift instruction register (Shift-IR) state, the JTAG TDO output can change earlier than expected.

Release Date

2023-12-13

Revision

1.0 English