Description

000035447 - Design Advisory - 2023.1.x (and prior) Vivado and Versal - timing of bypass BLI setup path and BUFGCTRL cascade are incorrect

Release Date
2023-10-19
Revision
1.0 English

In the Versal families there is a Boundary Logic Interface register (BLI) that exists between the resources in and beside the XPIO and programmable logic regions to help optimize the timing of an interface.


The BLI also exists between the AI Engines and the programmable logic regions to help optimize the timing of those interfaces.

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In 2022.1.x and prior versions of Vivado, if the BLI is bypassed for the paths listed in the table below, Vivado timing incorrectly analyzes the setup path, and is missing 250ps. 



Table : Path Impacted by incorrect Setup Timing when BLI is bypassed 
 
XPHY (RIU_WR_DATA[15:0], RIU_WR_EN)
XPLL (DI[4:0], PSEN, PSINCDEC, PWRDOWN)
MMCM (CLKINSEL, DADDR[3:0], DI[3:0], PSEN, PSINCDEC, PWRDWN)
DPLL (DADDR[3:0], DI[3:0], PSEN, PSINCDEC, PWRDWN)
BUFGCTRL (not all sites) (CE0, CE1, S1)
BUFGCE_DIV (not all sites) (CE, CLR)
AIE_PL_M_TREADY[5:0], AIE_PL_S_TVALID[5:0], AIE_PL_TRIG_0_IN[15:0], AIE_PL_TRIG_1_IN[15:0]



In Versal architecture, BUFGCTRL multiplexers and all derivatives can be cascaded to adjacent clock buffers to create larger multiplexers.


In 2023.1.x and prior versions of Vivado, if the BUFGCTRL is used in a cascade, the timing of the clock net in the cascade is incorrect, in the magnitude of 90ps too large. As a result, a retiming of that clock network is required.