Description

000035288 - Design Advisory for Versal MRMAC - Vivado 2023.1/2023.1.1/2023.1.2 – Missing Timing arcs on some devices and configurations

Release Date
2023-08-29
Revision
1.0 English

In Vivado 2023.1, 2023.1.1 and 2023.1.2, there is an issue with the MRMAC timing model which will cause unreported timing violations on some interface signals (for example, RX_SERDES_DATA bits) when the IP is configured in Static mode.

These timing violations can result in failures of the MRMAC data paths or PTP signaling.

In Vivado 2023.1, the MRMAC is missing timing arcs for the following devices:

  • XCVP1052 
  • XCVC2802 
  • XCVE2302 
  • XCVP2502 
  • XCVP2802 

In Vivado 2023.1.1 and 2023.1.2 the Versal MRMAC is missing timing arcs for the following devices:

  • XCVE2302 
  • XCVP2502 
  • XCVP2802