000035288 - Design Advisory for Versal MRMAC - Vivado 2023.1/2023.1.1/2023.1.2 – Missing Timing arcs on some devices and configurations - In Vivado 2023.1, 2023.1.1 and 2023.1.2, there is an issue with the MRMAC timing model which will cause unreported timing violations on some interface signals (for example, RX_SERDES_DATA bits) when the IP is configured in Static mode. These timing violations can result in failures of the MRMAC data paths or PTP signaling.

Release Date

2023-08-29

Revision

1.0 English