000034465 - Deisgn Advisory for 2022.2 (and earlier) Vivado: Versal incorrect timing parameter for LVCMOS and LVDCI when CCIO is driving BUFGCE and IBUFDS_DISABLE IBUFDISABLE to O

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In the 2022.2 version of Vivado and earlier, when the I/O is a CCIO and the input is used to drive BUFGCE, the timing parameter used for the IOSTANDARDs of LVCMOS and LVDCI is over reporting the delay through the input buffer.

If you are using a CCIO with the LVCMOS or LVDCI driving a BUFGCE and you are doing a static timing closure (i.e. using a set_input_delay) for I/Os capturing data with the BUFGCE, the timing report will be incorrect. This could result in incorrect data capture.

In addition, the timing path for the IBUFDS_IBUFDISABLE path from IBUFDISABLE to O for the differential standard has incorrect timing information and therefore this path is not timed correctly in Vivado.

This issue was found in the 2021.1 version, but applies to all Vivado versions supporting Versal families.