This issue affects UltraScale+ designs using Dynamic Function eXchange (DFX) and using Vivado version 2022.1 and older.
Tandem with Field Updates designs can also be affected as this flow uses DFX to load partial bitstreams, but a standard Tandem without DFX would not be affected.
This issue has not been reported for the Versal architecture. If similar behavior is found for a Versal Device not related to the decoupling and pr_verify suggestions, please contact technical support.
A design DFX will have hardware failures that appear to be consistent but have a low rate of failure.
The issue is in the write_bitstream process and relates to maintaining static route stability within the expanded routing regions.
Symptoms:
While loading partial bitstreams, static glitches are seen. For example, a design has multiple RMs A, and B, and RM A is initially loaded. Only when loading a different RM (RM B) does the glitch occur. The issue is not seen when moving from a black box to a full RM or vice versa.
The hardware failures have been found to be an Interconnect (INT) tile contention issue. Affected software has not enforced a DFX interface routing rule for a net with both static and RM loads. The problem cannot be viewed from the Vivado Device View or via Tcl.
Identification:
Please use the following steps to rule out issues not related to this answer record.
- Confirm that proper logic decoupling has been used. More information on decoupling can be found in the DFX User Guide UG909
- Use pr_verify to make sure there are no static differences
- Taking all fully routed design checkpoints (DCP) from a previous version, and opening this in Vivado 2022.2
- Writing out the full and partial bitstreams
- Re-testing the same bitstream loading under the same conditions that had previously failed. The migrated DCPs DO NOT need to be re-routed or implemented.