The Interrupt Status (IS) register is shown in Figure 1. This register combined with the IE, IP, MIS, and MIE registers define the interrupt interface of the subsystem. The Interrupt Status register uses one bit to represent each internal subsystem interruptible condition. One of these interruptible conditions, register Access Complete (HardAcsCmplt), comes from the TEMAC component and is further defined and enabled by the MIS and MIE registers, which are described in Interrupt Status Register and Interrupt Enable Register.
When an interruptible condition occurs, it is captured in this register (represented as the corresponding bit being set to 1) even if the condition goes away. The latched interruptible condition is cleared by writing a 1 to that bit location. Writing a 1 to a bit location that is 0 has no effect. Likewise, writing a 0 to a bit location that is 1 has no effect. Multiple bits can be cleared in a single write.
Whenever any bits are set in the Interrupt
Pending register, the interrupt signal is driven active-High out of the AXI
Ethernet Subsystem. The following figure shows the structure of the interrupt register.
The following figure shows the Interrupt Status register bit definitions.
| Bits | Name | Access | Reset Value | Description |
|---|---|---|---|---|
| 31:9 | Reserved | RO | 0x0 | Reserved: These bits are reserved for future use and always return zero. |
| 8 | PhyRstCmplt | R/W | 0 | PHY Reset Complete. When set to 1, this bit indicates the PHY can
be accessed. This signal does not transition to 1 for 5 ms after PHY_RST_N transitions
to 1.
|
| 7 | MgtRdy 1 | R/W | 0 / 1 |
Serial Transceiver Ready: This bit indicates if the
TEMAC core is out of reset and ready for use. In systems that use a serial
transceiver, this bit goes to 1 when the serial transceiver is ready to use. Prior to
that time, access of TEMAC core registers does not complete and the subsystem does not
operate. In systems that do not use a serial transceiver, this signal goes to 1
immediately after reset.
|
| 6 | RxDcmLock | R/W | 1 |
Receive DCM Lock: No longer used, but reserved for
future use. This bit is always one.
|
| 5 | TxCmplt | R/W | 0 |
Transmit Complete: This bit indicates that a frame
was successfully transmitted.
|
| 4 | RxMemOvr | R/W | 0 |
Receive Memory Overrun: This bit indicates that the
receive Memory overflowed while receiving an Ethernet frame.
|
| 3 | RxRject 2 | R/W | 0 |
Receive Frame Rejected: This bit indicates that a
receive frame was rejected.
|
| 2 | RxCmplt | R/W | 0 |
Receive Complete: This bit indicates that a packet
was successfully received.
|
| 1 | AutoNeg | R/W | 0 |
Auto-Negotiation Complete: This bit indicates that
auto-negotiation of the SGMII or 1000BASE-X interface has completed.
|
| 0 | HardAcsCmplt | R/W | 0 |
Hard register Access Complete: This bit indicates
that an access of the TEMAC component has completed.
|
|
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