A high-level block diagram of the AXI Ethernet Subsystem is shown in the following figure.
The subsystem provides an AXI4-Lite bus interface for a simple connection to the processor core to allow access to the registers. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers). 32-bit AXI4-Stream buses are provided for moving transmit and receive Ethernet data to and from the subsystem. These buses are designed to be used with an AXI Direct Memory Access (DMA) IP or AXI Multichannel Direct Memory Access (MCDMA) IP core, AXI4-Stream Data FIFO, or any other custom logic in any supported device. The AXI4-Stream buses are designed to provide support for TCP/UDP partial or full checksum offload in hardware if required. The AXI4-Stream buses are described in Frame Transmission.
The PHY side of the subsystem is connected to an off-the-shelf Ethernet PHY device, which performs the BASE-T standard at 1 Gb/s, 100 Mb/s, and 10 Mb/s speeds. The PHY device can be connected using any of the following supported interfaces: GMII/MII, RGMII, or, by using the 1G/2.5G Ethernet PCS/PMA or SGMII module.
A 1000BASE-X PHY can be implemented directly in the FPGA using the 1G/2.5G Ethernet PCS/PMA or SGMII module configured in 1000BASE-X mode. This can be connected directly to an external optical module.
The AXI 1G/2.5G Ethernet subsystem can be configured in non-processor mode where the buffer module is not present. In this mode, all of the ports and interfaces are directly connected to the TEMAC and the PCS PMA. Non-processor mode can be enabled only for SGMII or 1000BASE-X.
The supported physical interface types are:
- GMII
- The Gigabit Media Independent Interface (GMII) is defined by the IEEE 802.3 specification; it can provide support for Ethernet operation at 10 Mb/s, 100 Mb/s, and 1 Gb/s speeds.
- MII
- The Media Independent Interface (MII) is defined by the IEEE 802.3 specification; it can provide support for Ethernet operation at 10 Mb/s and 100 Mb/s speeds.
- RGMII
- The Reduced Gigabit Media Independent Interface (RGMII) is, effectively, a Double Data Rate version of GMII; it can provide support for Ethernet operation at 10 Mb/s, 100 Mb/s, and 1 Gb/s speeds.
- 1000BASE-X
- Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) operation, as defined in the IEEE 802.3-2008 standard.
- GMII to Serial-GMII (SGMII) Bridge
- As defined in the Serial-GMII specification (ENG-46158).
- Both
- This feature is to support switching between the 1000BASE-X and SGMII standard. see the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).
In AVB mode, Ethernet AVB Endpoint is selected which is designed to meet the following IEEE specifications.
- IEEE802.1AS
- Supports clock master functionality, clock slave functionality and the Best Master Clock Algorithm (BMCA).
- IEEE802.1Qav
- Supports arbitration between different priority traffic and implements bandwidth policing.
The following infrastructure cores are used by the AXI Ethernet Subsystem:
- Tri-Mode Ethernet MAC core
- 1G/2.5G Ethernet PCS/PMA or SGMII core
- AXI Ethernet Buffer: Features such as TX and RX TCP/UDP Partial Checksum offload, IPv4 TX and RX TCP/UDP full checksum offload, TX and RX VLAN stripping, tagging and Extended filtering for multicast frames are provided using this infrastructure core. The details related to these features are described in this document.
- Timer Synchronization core (Timer Sync): This core synchronizes the timer in the selected format from the system clock domain into the subsystem clock domain.