Revision History - 7.1 English

Peak Cancellation Crest Factor Reduction LogiCORE IP Product Brief (PB008)

Document ID
PB008
Release Date
2022-04-20
Version
7.1 English

The following table shows the revision history for this document.

Date

Version

Description of Revisions

04/20/2022

7.1

Added support for super sampling rate WCFR standalone mode.

10/22/2021

7.0

Core's control interface address format is modified to support 8MB of space.

Added support for Zynq UltraScale+ RFSoC DFE devices to use DFE-CFR Primitives.

Updated Features section.

Deprecated use of Data Rate = 8 when using PL CFR.

01/08/2021

6.4

Extended the LUT optimization features available for CPS=2 in PC-CFR v6.3 to all CPS cases. These optimizations must be seen in all smart peak processing cases.

05/22/2019

6.3

Enabled LUT optimization for SPP and Data Rate (clock-cycles/samples) = 2 scenarios at the cost of 3 DSP48s increase per iteration.

12/05/2018

6.2

Updated the Features section with a description of Dynamic mode.

06/20/2018

6.2

Added 16 antenna support.

DSP48 optimization in CPGs.

Core is fully supported in Vivado 2018.2.

10/05/2016

6.1

Added support to work as Stand-alone Hard Clipper.

Added optional feature to operate WCFR without smart peak processing.

Added TUSER forwarding feature.

Added Support for two more RATs (RATD and RATE) in dynamic CP computation mode.

11/18/2015

6.0

Added support for UltraScale+ families.

04/01/2015

6.0

Production release of PC-CFR v6.0 core.

10/01/2014

6.0

Version 6.0 is Early Access, Lounge delivered to customers.

Added UltraScale Architecture support.

Updated Features.

Removed resource table and replaced with link to product page.

12/18/2013

5.0

Revision number advanced to 5.0 to align with core version number.

Added dynamic support (dynamic power variation and frequency hopping)

Hard clipper support

Change in tool settings for characterization

New TUSER port added in Dynamic mode

03/20/2013

3.0

PC-CFR v4.0 is available only with Vivado; other changes are

Improved fmax, core can be clocked at 491.52 MHz for -2 devices

Core latency has changed 

12/18/2012

2.0

Updated for 2012.4/14.4.

Real/Complex CP selection added

Number of CPGs/iteration increased to 12

Core is fully supported in Vivado 2012.4

Peak detect window is used in place of allocator spacing

06/22/2011

1.0

Initial Xilinx release. Previous version of this Product Brief is XMP039.