Features - 7.1 English

Peak Cancellation Crest Factor Reduction LogiCORE IP Product Brief (PB008)

Document ID
Release Date
7.1 English

The common features of the PC-CFR core and individual configuration features of both implementations of PC-CFR (using PL resources only and using DFE-CFR + PL resources) are as follows:

Support for multiple air interface standards.

Smart Peak Processing mode for supporting wide transmit bandwidth up to 400 MHz, processes incoming samples at >1.2 times instantaneous bandwidth (iBW) reducing resource utilization.

Support for power and frequency dynamics.

For additional features see Features (cont.).

LogiCORE IP Facts Table

Core Specifics

Supported Device Family(1)

Zynq® UltraScale+™ RFSoC DFE
UltraScale+™ Families

UltraScale™ Architecture
Zynq®  UltraScale+ Devices

7 series FPGAs

Supported User Interfaces

AXI4-Stream, AXI4-Lite

Provided with Core

Design Files

Encrypted RTL

Example Design

Not Provided

Test Bench


Constraints File

Vivado XDC

Simulation Model

VHDL and Verilog Structural Simulation Model

MATLAB® Model available

S/W Driver

CFR Reference Design available at www.xilinx.com/products/intellectual-property/ef-di-pc-cfr.html

Tested Design Flows(2)

Design Entry

Vivado® Design Suite


For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.


Vivado Synthesis


Release Notes and Known Issues

Master Answer Record: 54486

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

 Xilinx Support web page


1.For a complete listing of supported devices, see the Vivado IP catalog.

2.For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.