Video Format Bridge (VFB) Latency - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)
Document ID
PG232
Release Date
2023-11-06
Version
5.4 English

The VFB core latency is the time from the VFB input stream interface tvalid to VFB output stream interface tvalid .

The following table provides the latency numbers for various core configurations.

Table 1. VFB Latency
Data Type Pixel Mode Line Rate Latency in rxbyteclk Latency in Video Clock
RAW20 Single 1000 10 24
RAW8 Single 1000 1 3
RAW8 Dual 1000 1 3
RAW8 Quad 1000 1 4
RAW10 Single 1000 2 6
RAW10 Dual 1200 3 6
RAW10 Quad 800 1 3
YUV 422-8Bit Quad 2000 16 9
  1. All the calculations are made for a fixed video clock of 148 MHz.

The following table provides the overall latency numbers of MIPI CSI-2 RX Subsystem for various core configurations.

Table 2. MIPI CSI-2 RX Subsystem Latency
Data Type Pixel Mode Line Rate Latency in rxbyteclk
RAW20 Single 1000 61
RAW8 Single 1000 48
RAW8 Dual 1000 48
RAW8 Quad 1000 48
RAW10 Single 1000 53
RAW10 Dual 1200 59
RAW10 Quad 800 47
YUV 422-8Bit Quad 2000 92
  1. All the calculations are made for a single lane design with a fixed video clock of 148 MHz.
  2. The latency is improved by increasing the number of lanes.
  3. Overall latency in micro seconds (μ s) can be calculated from the data provided in this table.

    For RAW8 Single pixel mode with a line rate of 1000 Mbps, rxbyteclk in MHz (Line rate/8) = 1000/8 = 125 MHz

    Latency in μ s (Latency in rxbyteclk * rxbyteclk period) = 48*(1/125 MHz) = 0.384 μs.