Shared Logic Outside Subsystem - 5.4 English - PG232

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)
Document ID
PG232
Release Date
2023-11-06
Version
5.4 English

The PLLs are outside this subsystem instance.

Select Include Shared Logic in example design if this is not the first MIPI CSI-2 RX Subsystem instance in a multi-subsystem design that shares PLLs generated from other MIPI CSI-2 RX Subsystem that is configured with shared logic in the Core mode.

To fully use the PLL, customize one MIPI CSI-2 RX Subsystem with shared logic in the subsystem and one with shared logic in the example design. You can connect the PLL outputs from the first MIPI CSI-2 RX Subsystem to the second subsystem.

There should be at least one MIPI CSI-2 RX Subsystem with Include shared Logic in the Core mode whose outputs for shared resources can be used in other MIPI CSI-2 RX Subsystem generated with Include shared logic in example design mode.

The following figure shows the sharable resource connections from the MIPI CSI-2 RX Subsystem with shared logic included (MIPI_CSI_SS_Master) to the instance of another MIPI CSI-2 RX Subsystem without shared logic (MIPI_CSI_SS_Slave00 and MIPI_CSI_SS_Slave01) for AMD UltraScale+ devices.

Figure 1. Shared Logic in the Example Design
Note: The master and slave cores can be configured with different line rates when operating at less than 1500 Mb/s. However, when operating at greater than 1500 Mb/s with the Deskew detection feature enabled, the master and slave cores should be configured with the same line rate when sharing clkoutphy within the IO bank. There must be at least one core in master mode in a system whose clocks can be shared with slave mode cores.
Figure 2. Clock Sharing in MIPI CSI-2 TX and MIPI CSI-2 RX Subsystems
Important: MIPI CSI-2 TX Subsystem and MIPI CSI-2 RX Subsystem share clocking resources, in such scenario MIPI CSI-2 TX Subsystem need to be configured using Include Shared Logic in Core option under Shared Logic tab. However, for line rates>1500, MIPI CSI-2 RX Subsystem has additional ports called "rxbyteclkhs_cnts_in/rxbyteclkhs_cnts_out." Hence, MIPI CSI-2 TX Subsystem and MIPI CSI-2 RX Subsystem cannot share clocking resources for cases of line rates>1500.
Important: For line rates <= 1500, the master and slave can be configured with the different line rate when sharing clkoutphy within IO bank.
Important: For line rates > 1500, the controller and the target should be configured with the same line rate when sharing clkoutphy within the IO bank.