Running the Design on Hardware

Important: Before running the design on the Hardware, you need to build the project and generate the required bit/elf files. See Implementing the Example Design for more details.

Connect the JTAG cable and USB-UART cable to the board.
Go to the Application Example Design Project directory.
```
Example: cd ./<IP instance name>_ex
```
Launch the Xilinx System Debugger by selecting Start > All Programs > Xilinx DesignTools > Vivado > Vivado Tcl Shell .
Invoke Xilinx System Debugger.
```
(xsdb)Vivado% xsdb
```
Establish connections to debug targets.
```
xsdb% connect
```
List all available JTAG targets
```
xsdb% targets
```
Note: The target number for the PSU, PL, RPU, and Cortex-R5F might be different. Run the targets and ensure that they are using the correct target number.

Download the bitstream to the FPGA.

xsdb% fpga -file ./<ip_instance_name>_ex.runs/impl_1/design_1_wrapper.bit/design_1_wrapper.pdi

Set and reset the corresponding target processor.

xsdb % targets -set -filter {name =~ “Cortex-A53 #0”}/{name =~ “Cortex-A72 #0”}
xsdb % rst -processor

Download and start the application:
```
xsdb % dow -force
 vitis_workspace>/<platform_project>/zynqmp_fsbl/fsbl_a53.elf
```
Note: Skip the above step for SP701 or VEK280/VCK190-based example designs.
```
xsdb % dow -force
 <vitis_workspace>/xmipi_example_1/Debug/xmipi_example_1.elf
```
Run the application giving con command in xsdb promot.

Note: The corresponding application file for SP701 board based example designs is xmipi_sp701_1.elf , for VEK280 xmipi_vek280_1.elf and for a VCK190 board it is xmipi_vck190_1.elf .

Note: For the SP701 board-based example design, set target processor as MicroBlaze. For the VCK190 board based example design, set the target processor as Cortex-A72.
For the ZCU102 board based example design, to observe the results, start a Hyper Terminal program on the host PC and configure its serial port (Interface 0) to 115200 baud rate with the default configuration. Ensure that the UART cable is connected to the board and the PC. The UART console displays a menu in the console. You are prompted for design related inputs.
1. Initially, the application asks you if the camera sensor and display panel are connected. Enter either y or n .
  Note: If you answer n, it is assumed that the camera or the DSI panel or both are not available. The system displays the Camera sensor is set as Disconnected, and/or the DSI Display panel is set as Disconnected error message on the console.
2. Under the Main Menu, you are prompted for video source, display device, and resolution details.
  - Press s to select the Sensor as video source and show live sensor data capture.
  - Press t to select the Video Test Pattern generator as the video source and shows rainbow pattern on screen.
  - Press h to switch the display to HDMI monitor if not already displayed.
  - Press d to switch the display to DSI panel.
  - Press r to bring up the resolution menu.
    Note: Selecting an invalid option prompts an Unknown option error message on the console. All resolutions support only four lanes. The supported lane and other pipeline configurations are listed under the Current Pipe Configuration section displayed on the console.
For the SP701 board based Example Design, to observe the results, start a Hyper Terminal program on the host PC and configure its serial port (Interface 0) to 9600 baud rate with the default configuration. Ensure that the UART cable is connected to the board and the PC. The UART console displays a menu in the console. Under the Main Menu, you are prompted to select the preferred output.
1. Press 1 to select the display to DSI Panel
2. Press 2 to switch the display to HDMI Monitor
For the VCK190 board-based Example Design, to observe the results, start a Hyper Terminal program on the host PC and configure its serial port (Interface 0) to 115200 baud rate with the default configuration. Ensure that the UART cable is connected to the board and the PC. The UART console displays a menu in the console. Under the Main Menu, you are prompted to select the preferred output.
Figure 1. VCK190 and VEK280 Application Main Menu
- 0 - 1920x1080p60
- 1 - 3840x2160p60
Note: Selecting an invalid option prompts an Unknown option error message on the console. All resolutions support only four (4) lanes. The supported lane and other pipeline configurations are listed under the Current Pipe Configuration section displayed on the console.

Running the Design on Hardware - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)