Revision History - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

Document ID
Release Date
5.4 English
Section Revision History
11/06/2023 Version 5.4
Vitis Debugger Flow to Program FPGA Instead of XSDB Console. New Section.
Port Descriptions Updated.
VCK190 Hardware Setup Updated.
VEK280 Hardware Setup Updated.
05/16/2023 Version 5.3
VEK280 Setup Details New section.
MMCM Sharing Added information in the Shared Logic section.
10/19/2022 Version 5.2
General Updates Added new register to allow Dynamic VC selection.
04/26/2022 Version 5.1
General Updates Active_lanes port added when CSI-2 Controller Register Interface Disabled.
ZCU102 Application Example Design Overview Updated to support 4K60 on HDMI output.
11/17/2021 Version 5.1
Clocking Updated the examples.
Configuration Tab Updated Pixel Format and Included Video Format Bridge (VFB) options.
General Updates Updated MIPI CSI-2 RX Subsystem Application Example Design Block Diagram.
07/14/2021 Version 5.1
Tclk-Post Requirement New Section.
Designing with the Subsystem Added a new note for line rates that are >1500 in .
Configuration Tab Added a new parameter.
Running the Design on Hardware Updated.
Implementing the Example Design Updated.
Hardware Validation Updated.
General Updates Updated Vivado IDE Parameter to User Parameter Relationship.
01/08/2021 Version 5.1
General Updates
  • Corrections for Versal Adaptive SoC Support.
  • Added YUV420-8bit support.
Clocking Revised the examples.
07/16/2020 Version 5.0
General Updates Added support for Versal Adaptive SoC.
06/12/2020 Version 5.0
General Updates
  • Updated the register space information to include VCX Frame Error bit in the IER.
  • Updated the Interoperability testing for UltraScale+ devices.
  • Example Design for Vitis updated.
11/22/2019 Version 4.1
General Updates
  • Updated the register space information to include ISR and IER bits for skewcalhs.
  • Added Application example design for SP701 board.
  • Added CSI2 Controller Register Interface GUI option to aid resource optimization.
  • Removed AXI IIC Option.
07/02/2019 Version 4.0
General Updates
  • Extended line rate support up to 2500 Mbps.
  • Added support for Deskew sequence detection at MIPI D-PHY for UltraScale+ devices.
  • Corrected the doc version.
05/22/2019 Version 4.0
General Updates
  • Updated the minimum video clock requirement in chapter 3.
  • Added MIPI CSI2 RX Subsystem Latency Calculation.
  • Corrected Data corruption for certain word counts during RAW20 data type reception.
12/05/2018 Version 4.0
General Updates
  • Updated video_out_tdest and emb_nonimg_tdest port size.
  • Updated Table 2-5 to include VCX Frame Error register, Image Information 1, and Image Information 2 Registers for VC4 to VC15.
  • Updated Table 1-1 to include RAW16, RAW20, and YUV 422 10 bit data types.
  • Updated Table 4-1 User Parameters.
  • Included new GUI options for MIPI CSI-2 Standard v2.0 compatibility in the Configuration Tab.
  • Updated examples in the Pixel Packing for Multiple Data Types section to match the alignment described in AXI4-Stream Video IP and System Design Guide (UG934).
04/04/2018 Version 3.0
General Updates
  • ECC and CRC of long packets are made available on TUSER ports of output stream interfaces.
  • Added support for additional 7 series devices.
  • Added dynamic configuration capability for IDELAY Tap values in fixed calibration mode of 7 series.
10/04/2017 Version 3.0
General Updates
  • Added Application Example Design to demonstrate a full end-to-end system from capture to display on ZCU102.
  • Added Board automation support for LI-IMX274MIPI-FMC V1.0 FMC model.
04/05/2017 Version 2.2
General Updates
  • Word Count (WC) corruption limited to current packet. Additional bit in ISR added to report this conditions.
  • MIPI DPHY v3.1 changes integrated.
11/30/2016 Version 2.1
General Updates
  • Added calibration mode parameters for FIXED and AUTO modes.
10/05/2016 Version 2.1
General Updates
  • MIPI D-PHY 3.0 changes integrated
  • Added 7 series support
04/06/2016 Version 2.0
General Updates
  • MIPI D-PHY 2.0 changes integrated
  • Shared logic support
  • Video Format Bridge core changes to support RAW8 and User Defined Byte-based Data at all times along with the Vivado IDE selected data type.
11/18/2015 Version 1.0
Initial Release N/A