The subsystem has two reset ports:
-
lite_aresetn: Active-Low reset for the AXI4-Lite register interface. -
video_aresetn: Active-Low reset for the subsystem blocks.
The duration of video_aresetn
should be a minimum of 40 dphy_clk_200M cycles to propagate the reset
throughout the system. See the following figure.
Figure 1. MIPI CSI-2 RX Reset
The following table summarizes all resets available to the MIPI CSI-2 RX Subsystem and the components affected by them.
| Sub-core | Lite_aresetn | Video_aresetn |
|---|---|---|
| MIPI CSI-2 RX Controller | Connected to s_axi_aresetn core port | Connected to m_axis_aresetn core port |
| MIPI D-PHY | Connected to s_axi_aresetn core port | Inverted signal connected to core_rst core port |
| Video Format Bridge | N/A | Connected to s_axis_aresetn core port |
| AXI Crossbar | Connected to aresetn core port | N/A |
Note: The effect of each reset
(
lite_resetn , video_aresetn ) is determined by the
ports of the sub-cores to which they are connected. See the individual sub-core product
guides for the effect of each reset signal.