Register Space - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

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5.4 English

This section details registers available in the MIPI CSI-2 RX Subsystem. The address map is split into following regions:

  • MIPI CSI-2 RX Controller core
  • MIPI D-PHY core

Each IP core is given an address space of 4K. Example offset addresses from the system base address when the MIPI D-PHY registers are enabled are shown in the following table.

Table 1. Sub-Core Address Offsets
IP Cores Offset
MIPI CSI-2 RX Controller 0x0_0000
MIPI D-PHY 0X0_1000