MIPI D-PHY - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

Document ID
Release Date
5.4 English

The MIPI D-PHY IP core implements a D-PHY RX interface and provides PHY protocol layer support compatible with the CSI-2 RX interface. The MIPI D-PHY IP core also supports the deskew pattern detection for line rates greater than 1500 Mbps. See the MIPI D-PHY LogiCORE IP Product Guide (PG202) for details. MIPI D-PHY implementation differs for the AMD UltraScale+ devices and the 7 series devices concerning I/O.

For UltraScale+ devices, the Vivado IDE provides a Pin Assignment Tab to select the required I/O. However, for the 7 series devices, the clock-capable I/O should be selected manually. In addition, the 7 series devices do not have native MIPI IOB support. You must target either HR bank I/O or HP bank I/O for the MIPI IP implementation. For more information on MIPI IOB compliant solution and guidance, refer to D-PHY Solutions (XAPP894) .