The MIPI CSI-2 RX Controller core consists of multiple layers defined in the MIPI CSI-2 RX, such as the lane management layer, low-level protocol, and byte to pixel conversion.
The MIPI CSI-2 RX Controller core receives 8-bit data per lane, with support for up to four lanes from the MIPI D-PHY core through the PPI. As shown in the following figure, the byte data received on the PPI is processed by the low-level protocol module to extract the real image information. The final extracted image is made available to the user/processor interface using the AXI4-Stream protocol. The lane management block always operates on 32-bit data received from PPI, irrespective of the number of lanes.
Features of this core include:
- 1–4 lane support, with register support to select active lanes (the actual number of available lanes to be used)
- Short and long packets with all word count values supported
- Primary and many secondary video formats supported
- Data Type (DT) interleaving
- Virtual Channel Identifier (VC) interleaving
- Combination of Data Type and VC interleaving
- Multi-lane interoperability
- Error Correction Code (ECC) for 1-bit error correction and 2-bit error detection in packet header
- CRC check for payload data
- Long packet ECC/CRC forwarding capability for downstream IPs
- Maximum data rate of 3200 Mbps pixel byte packing based on data format
- AXI4-Lite interface to access core registers
- Low power state detection
- Error detection (D-PHY Level Errors, Packet Level Errors, and Protocol Decoding Level Errors)
- AXI4-Stream interface with 32/64-bit TDATA width support to offload pixel information externally
- Interrupt support for indicating internal status/error information
As shown in the following table, the embedded non-image (with data type code 0x12) AXI4-Stream interface data width is selected based on the Data Type selected.
Data Type (DT) | AXI4-Stream Interface TDATA Width |
---|---|
RAW6 | 32 |
RAW7 | 32 |
RAW8 | 32 |
RAW10 | 64 |
RAW12 | 64 |
RAW14 | 64 |
RAW16 | 64 |
RAW20 | 64 |
All RGB | 64 |
YUV 420 8-bit | 64 |
YUV 422 8–bit | 64 |
YUV 422 10–bit | 64 |
Abrupt termination events such as a soft reset, disabling a core while a packet is being written to the line buffer, or a line buffer full condition results in early termination. The termination is implemented by the assertion of EOL on the video interface or TLAST and TUSER[1] on the embedded non-image interface, based on the current long packet being processed.
Null/Blanking packets are ignored by the MIPI CSI-2 RX Controller. No errors are reported in such cases, and the core continues with the next packet processing.