IP Facts - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

Document ID
PG232
Release Date
2023-11-06
Version
5.4 English
AMD LogiCORE™ IP Facts Table
Core or Subsystem Specifics
Supported Device Family 1 AMD Versal™ Adaptive SoC, AMD UltraScale+™ , AMD Zynq™ UltraScale+™ MPSoC, AMD Zynq™ UltraScale+™ RFSoC, AMD Zynq™ 7000 SoC, 7 seriesFPGAs
Supported User Interfaces AXI4-Lite, AXI4-Stream
Resources Performance and Resource Utlization web page
Provided with Core or Subsystem
Design Files Encrypted RTL
Example Design AMD Vivado™ IP Integrator
Test Bench Not Provided
Constraints File XDC
Simulation Model Not Provided
Supported S/W Driver 2 Standalone and Linux
Tested Design Flows 3
Design Entry AMD Vivado™ Design Suite
Simulation For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 65242
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the AMD Vivado™ IP catalog.
  2. Standalone driver details can be found in <install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers_api_toc.htm.

    Linux: Linux OS and driver support information is available from the Linux <Core Name> Driver Page.

  3. For the supported versions of third-party tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).