Global Interrupt Enable Register - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

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5.4 English

The Global Interrupt Enable register is described in the following table.

Table 1. Global Interrupt Enable Register (0x20)
Bits Name Reset Value Access Description
31–1 Reserved N/A N/A Reserved
0 Global Interrupt enable 0x0 R/W

Master enable for the device interrupt output to the system

1: Enabled—the corresponding Interrupt Enable register (IER) bits are used to generate interrupts

0: Disabled—Interrupt generation blocked irrespective of IER bits