The Global Interrupt Enable register is described in the following table.
| Bits | Name | Reset Value | Access | Description |
|---|---|---|---|---|
| 31–1 | Reserved | N/A | N/A | Reserved |
| 0 | Global Interrupt enable | 0x0 | R/W |
Master enable for the device interrupt output to the system 1: Enabled—the corresponding Interrupt Enable register (IER) bits are used to generate interrupts 0: Disabled—Interrupt generation blocked irrespective of IER bits |