Generic Short Packet Register - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

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5.4 English

The Generic Short Packet register is described in the following table. Packets received with generic short packet codes are stored in a 31-deep internal FIFO and are made available through this register. The following conditions reset the FIFO:

  • External reset on video_aresetn
  • Core disable or soft reset through register settings.

Note the following:

  1. If one-bit error occurs during data-transmission, the MIPI CSI-2 controller fixes the error-bit and stores generic short packet data into the FIFO.
  2. When a short packet is received with a 2-bit error, the MIPI CSI-2 controller discards the data without pushing the data to the FIFO.
  3. Because the data field of the register is only 16 bits wide, the ECC information is not stored.
Table 1. Generic Short Packet Register (0x30)
Bits Name Reset Value Access Description
31–24 Reserved N/A N/A Reserved
23–8 Data 0x0 R 16-bit short packet data
7–6 Virtual Channel 0x0 R Virtual channel number
5–0 Data Type 0x0 R Generic short packet code