General Design Guidelines - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

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5.4 English

The subsystem fits into a image sensor pipe receive path. The input to the subsystem must be connected to an image source such as an image sensor transmitting data that adheres to the MIPI protocol. The output of the subsystem is image data in AXI4-Stream format. Based on the throughput requirement the output interface can be tuned using customization parameters available for the subsystem.

Because the MIPI protocol does not allow throttling on the input interface, the module connected to the output of this subsystem should have sufficient bandwidth for the data generated by the image sensor.

The Protocol Configuration Register [1:0] can be used to dynamically configure the active lanes used by the subsystem using the following guidelines:

  1. Program the required lanes in the Protocol Configuration register (only allowed when “Enable Active Lanes” is set in the AMD Vivado™ IDE).
  2. The subsystem internally updates the new lanes information after the current packet complete indication is seen (that is, when the current active lanes indicate a Stop state condition) and a subsequent RxByteClkHS signal is seen on the PPI.
  3. A read from the Protocol Configuration register reflects the new value after the subsystem has successfully updated the new lanes information internally.
  4. Do not send the new updated lanes traffic until the read from Protocol Configuration registers reflects the new value.
  5. Initialize all MIPI interfaces in the same HP IO Bank at the same time. For example, multiple CSI-2 or D-PHY instances in a system. For more information on implementing multiple interfaces in the same HP IO Bank, see the UltraScale Architecture SelectIO Resources (UG571).