The MIPI D-PHY RX core latency is the time from the start-of-transmission (SoT) pattern on the serial lines to the active hs signal assertion on the PPI. The HS_SETTLE period contributes significantly in the D-PHY latency calculation.
The following table provides the latency numbers for various core configurations.
| Data Type | Pixel Mode | Line Rate |
Latency in rxbyteclk (HS_SETTLE + Internal latency) |
|---|---|---|---|
| RAW20 | Single | 1000 | 26(23+3) |
| RAW8 | Single | 1000 | 26(23+3) |
| RAW8 | Dual | 1000 | 26(23+3) |
| RAW8 | Quad | 1000 | 26(23+3) |
| RAW10 | Single | 1000 | 26(23+3) |
| RAW10 | Dual | 1200 | 30(26+4) |
| RAW10 | Quad | 800 | 22(20+2) |
| YUV 422-8Bit | Quad | 2000 | 44 |
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