The subsystem clocks are described in the following table. Clock frequencies should be selected to match the throughput requirement of the downstream video pipe IP cores.
Clock Name | Description |
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lite_aclk | AXI4-Lite clock used by the register interface of all IP cores in the subsystem. |
video_aclk | Clock used as core clock for all IP cores in the subsystem. |
dphy_clk_200M | See the MIPI D-PHY LogiCORE IP Product Guide (PG202) for information on this clock. |
clkoutphy_out |
The clkoutphy_out signal is generated within the PLL with 2500 Mbps line rate when the Include Shared logic in core option is selected.
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clkoutphy_in | The clkoutphy_in signal should be connected to the clkoutphy_out signal generated when the Include Shared logic in core option is selected. |
rxbyteclkhs_cnts_out | The rxbyteclkhs_cnts_out is the continuous clock signal generated within the PLL with the same frequency as rxbyteclkhs when the Include Shared logic in core option is selected and line rates are greater than 1500 Mbps. |
rxbyteclkhs_cnts_in | The rxbyteclkhs_cnts_in signal should be connected to the rxbyteclkhs_cnts_out signal generated when the Include Shared logic in example design option is selected and line rates are greater than 1500 Mbps. |
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