Clock Lane Information Register - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)

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5.4 English

The Clock Lane Information register is described in the following table. The Stop state is captured in this register.

Table 1. Clock Lane Information Register (0x3C)
Bits Name Reset Value Access Description
31–2 Reserved N/A N/A Reserved
1 Stop state 0x0 R Stop state on clock lane
0 Reserved N/A N/A Reserved