Application Example Design - 5.4 English

MIPI CSI-2 Receiver Subsystem LogiCORE IP Product Guide (PG232)
Document ID
PG232
Release Date
2023-11-06
Version
5.4 English

This chapter contains step-by-step instructions for generating an MIPI CSI-2 RX Subsystem application example design from the MIPI CSI-2 RX Subsystem by using the AMD Vivado™ flow.

Table 1. Hardware Details of the Application Example Design
Topology Hardware Processor Lanes, Line-rate, and Data Type
MIPI Video Pipe Camera to Display
  • ZCU102 Rev 1.0
  • AUO display panel (B101UAN01.7_H/W 1A)
  • LI-IMX274MIPI-FMC camera sensor module
  • HDMI monitor supporting 4K@60 fps with at least 12 bpc color depth
 AMD Zynq™ MPSoC

4 Lanes

1440 Mb/s Lane

RAW10
MIPI Video Pipe Camera to Display
  • SP701 Rev 1.1
  • AUO display panel(B10UAN01.7_H/W 1A))
  • PCAM-5C camera sensor module
  • HDMI Monitor
 MicroBlaze

2 Lanes,

420 Mb/s Lane

RAW10
MIPI Video Pipe Camera to Display
  • VCK190/VEK280
  • AUO Display Panel (B10UAN01.7_H/W 1A)
  • LI-IMX274MIPI-FMC camera sensor module
  • HDMI monitor supporting 4K@30fps with at least 12 bpc color dept
 AMD Versal™ adaptive SoC Control, Interfaces, and Processing System

4 Lanes

1440 Mb/s Lane

RAW10